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| W89C841F/D 3-IN-1 10/100M FAST ETHERNET CONTROLLER W89C841F/D 3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller -1- Publication Release Date: October 18, 2001 Revision A3 W89C841F/D The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes of W89C841F-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. PC, AT and IBM are registered trademarks of International Business Machines, Inc. DOS and Windows are registered trademarks of Microsoft corporation. All other trademarks mentioned in this document are property of their respective owners. For additional information or questions, please contact: Winbond Electronics Corp. -2- W89C841F/D Table of Contents1. GENERAL DESCRIPTION.......................................................................................................................... 4 2. FEATURES ................................................................................................................................................. 4 3. PIN CONFIGURATIONS............................................................................................................................. 6 4. PIN DESCRIPTION..................................................................................................................................... 9 PCI Interface.............................................................................................................................................. 9 Power Management Interface ................................................................................................................. 14 BootROM/Flash and EEPROM Interface ................................................................................................ 15 Transceiver Interface............................................................................................................................... 19 LED Interface........................................................................................................................................... 20 Configuration and Test Interface ............................................................................................................. 20 Power Pins .............................................................................................................................................. 20 5. BLOCK DIAGRAM .................................................................................................................................... 23 6. SYSTEM DIAGRAM.................................................................................................................................. 24 7. FUNCTIONAL DESCRIPTION.................................................................................................................. 25 Operation Mode Configuration ................................................................................................................ 25 Direct Memory Access Function.............................................................................................................. 25 Media Access Control (MAC) Function ................................................................................................... 26 Full Duplex and Half Duplex Function ..................................................................................................... 26 Network Media Speed Function .............................................................................................................. 26 Flow Control in Full Duplex Mode............................................................................................................ 26 Priority Tagged Frame Supporting QOS.................................................................................................. 26 EEPROM Auto-load and Software Programming Function ..................................................................... 27 BootROM Read and Flash Programming Function ................................................................................. 30 MII Management Function ....................................................................................................................... 32 System Resource Configuring................................................................................................................. 32 Power Management Function.................................................................................................................. 33 8. CONFIGURATION REGISTERS .............................................................................................................. 33 Configuration Register Mapping .............................................................................................................. 34 9. FUNCTION REGISTERS .......................................................................................................................... 47 Cxx Function Registers ........................................................................................................................... 47 Dxx Function Registers ........................................................................................................................... 62 MII Management Registers ..................................................................................................................... 79 10. ELECTRICAL CHARACTERISTICS ....................................................................................................... 90 Absolute Maximum Ratings..................................................................................................................... 90 Power Supply .......................................................................................................................................... 90 DC Characteristics................................................................................................................................... 90 AC Characteristics................................................................................................................................... 91 11. PACKAGE DIMENSIONS ..................................................................................................................... 100 W89C841F: 128L QFP (14 x 20 x 2.75 mm footprint 3.2 mm) .............................................................. 100 W89C841D: 128L LQFP (14 x 20 x 1.4 mm)......................................................................................... 101 -3- Publication Release Date: October 18, 2001 Revision A3 W89C841F/D 1. GENERAL DESCRIPTION W89C841F is a highly integrated PCI Fast Ethernet MAC controller with embedded Ethernet transceiver for 100BaseTX, 100BaseFX and 10BaseT. It is compliant with IEEE 802.3, 802.3u specification. Auto cross-over function is supported on TP terminal and the network status of W89C841F is indicated by 3 LED pins. W89C841F supports full/half duplex, asymmetrical flow control operation compliant with IEEE 802.3x and VLAN tagged frame compliant with IEEE 802.1p. According to different applications, W89C841F can be configured into one of 3 modes to operate by setting the pins CONFIG[1:0] and ModeSel[2:0] after power-on reset. The 3 operational modes of W89C841F are listed as below. 1. PCI Ethernet MAC controller with internal Ethernet PHYceiver. 2. Pure PCI Ethernet MAC Controller 3. Pure 10/100M PHYceiver W89C841F provides a host bus interface complying with the PCI local bus specification R2.2, Mini PCI Specification R1.0 and CardBus. W89C841F plays as a bus master role to improve network performance and reduce the bus utilization. There are built-in 2K bytes TX FIFO and 2K bytes RX FIFO to store data. The DMA controller handles the data transfer between the host memory and the FIFOs. The data received from network are queued into the RX FIFO then directly moved into the host memory through the PCI bus. On the other hand, the transmitted data are fetched from the host memory and directly queued into the transmit FIFO. No extra on-board memory is needed for data buffering during operation. For PC99/2001, W89C841F implements power management function that are compliant with Advanced Configuration and Power Interface (ACPI) specification R1.0, PCI Power Management Interface specification R1.1 and Network Device Class Power Management Reference specification V1.0a. W89C841F supports D3cold power management state if auxiliary power is detected. 3 types of wakeup events are acceptable like link status change, Magic Packet and 5 sets of wake-up frames. EEPROM (93C46) is supported by W89C841F to store configuration and Vital Product Data (VPD) information. The length of VPD information is up to 64 bytes. W89C841F can access the CardBus information Structure (CIS) information that is stored at EEPROM (93C56) or BootROM. W89C841F also supports BootROM/Flash interface to read/write BootROM or Flash memory. 2. FEATURES * Integrated Fast Ethernet MAC controller with10/100M Ethernet transceiver in one chip * Supports MII interface for programmable single PHYceiver or single MAC controller * Complies with IEEE 802.3, 802.3u specification * Supports 10BAST-T, 100BASE-TX and 100BASE-FX * Supports auto cross-over operation * Supports half duplex and full duplex for 10/100M operation * Supports flow control for full duplex mode compliant with IEEE 802.3x -4- W89C841F/D * Complies with IEEE802.3ac, 802.1Q for VLAN-tagged frame * Supports LED pins for network activity indication * Configurable to PCI, MiniPCI or CardBus bus interface * Supports PCI/MiniPCI bus master mode for DMA operation, fully compliant with PCI Local Bus Specification R2.2 and Mini PCI Specification R1.0 * Supports CardBus Information Structure (CIS) * Supports 25 to 33 MHz PCI clock speed * Compliant with APCI R1.0, PCI power management R1.1 and Network device Class Power management Reference specification V1.0a * Supports power management event asserted from D3(cold) device state with auxiliary power existing * Supports wakeup function for Link status change, Magic Packet and 5 sets of wakeup frames * Supports Vital Product Data (VPD) data structure up to 64 Bytes * Supports 2 sets of independent embedded 2K bytes FIFO for transmit and receive * Flexible multicast address filtering modes - 64-bit hash-table - All multicast and promiscuous * Supports 25 MHz crystal or oscillator as internal clock source * Provides EEPROM (93C46 or 93C56) to store configuration parameters, VPD, and CIS information * Supports 8KB to 256 KB BootROM interface for both PROM and Flash memory * 3.3V powered I/Os with 5V tolerant inputs * Packaged in 128-pin PQFP for W89C841F/ LQFP for W89C841D -5- Publication Release Date: October 18, 2001 Revision A3 3. PIN CONFIGURATIONS BTDATA4/DISFEFI BTDATA3/SELFX BTDATA2/EEDO BTDATA1/EEDI BTDATA0/EECK EECS VCC GND PWGD STK_RSTB CLKRUNB WOL/CSTSCHG INTAB PCI_RSTB PCICLK GND VCC_Core GNTB REQB PMEB AD31 AD30 AD29 AD28 AD27 VCC 128 125 120 115 110 105 103 1 100 5 95 10 90 102 15 W 89C841F (Integrated) 85 Figure 1. W89C841F Pin Configuration (Integrated) -620 25 30 35 38 40 45 50 55 60 64 VCC BTADD11 BTADD10 BTADD9 BTADD8 BTADD7 BTADD6 BTADD5 BTADD4 BTADD3 BTADD2 BTADD1 BTADD0 GND VCC_Core AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND VCC C_BEB0 80 75 GND AD26 AD25 AD24 C_BEB3 IDSEL AD23 AD22 AD21 VCC GND AD20 AD19 AD18 AD17 AD16 C_BEB2 FRAMEB IRDYB VCC GND TRDYB DEVSELB STOPB PERRB SERRB PAR C_BEB1 AD15 VCC GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 70 65 BTDATA5/ModeSel[0] BTDATA6/ModeSel[1] BTDATA7/ModeSel[2] BTCSB BTOEB/AUXPWR BTWEB/EESEL OSC/X1 X2 GNDA VCCA2 CONTROL VREF RTX GNDA VCC3A VCCA2 TP/FXIN TP/FXIP GNDA TP/FXON TP/FXOP GND VCC_Core LED_LNKACT LED_SPD LEDDUPCOL CONFIG1 CONFIG0 SCAN_EN BTADD17 BTADD16 GND VCC_Core BTADD15 BTADD14 BTADD13 BTADD12 GND W89C841F/D W89C841F/D Pin Configurations, continued 102 100 95 90 85 80 75 70 NC NC EEDO EEDI EECK EECS VCC GND PWGD STK_RSTB CLKRUNB WOL/CSTSCHG INTAB PCI_RSTB PCICLK GND VCC_Core GNTB REQB PMEB AD31 AD30 AD29 AD28 AD27 VCC 103 105 65 ModeSel[0] ModeSel[1] ModeSel[2] NC AUXPWR EESEL NC NC GNDA VCCA2 CONTROL NC NC GNDA VCC3A VCCA2 NC NC GNDA NC NC GND VCC_Core LINK SPEED DUPLEX CONFIG1 CONFIG0 SCAN_EN RXD3 RXD2 GND VCC_Core RXD1 RXD0 RXDV RXCLK GND 64 60 110 55 115 120 W 89C841F (MAC Controller) 50 45 125 40 128 VCC RXER TXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS MDIO MDC GND VCC_Core AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND VCC C_BEB0 10 15 20 25 30 35 Figure 1. W89C841F Pin Configuration (MAC Controller) GND AD26 AD25 AD24 C_BEB3 IDSEL AD23 AD22 AD21 VCC GND AD20 AD19 AD18 AD17 AD16 C_BEB2 FRAMEB IRDYB VCC GND TRDYB DEVSELB STOPB PERRB SERRB PAR C_BEB1 AD15 VCC GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 -7- Publication Release Date: October 18, 2001 Revision A3 38 1 5 Pin Configurations, continued DISFEFI SELFX NC NC NC NC VCC GND PWGD STK_RSTB NC NC NC PHY_RSTB PCICLK GND VCC_Core GNTB NC NC NC NC NC NC NC VCC 128 102 100 5 95 10 90 125 120 115 110 105 103 1 15 W 89C841F (PHYceiver) 85 Figure 1. W89C841F Pin Configuration (PHYceiver) -820 25 30 35 38 40 45 50 55 60 64 VCC RXER TXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS MDIO MDC GND VCC_Core RECFUL REC100 RECAN XOVEN PAUREC PHYA0 PHYA1 PHYA2 GND VCC NC 80 75 GND NC NC NC NC IDSEL NC NC NC VCC GND NC NC NC NC NC NC NC NC VCC GND NC NC NC NC CN NC NC NC VCC GND NC NC NC PWRDN INT PHYA4 PHYA3 70 65 ModeSel[0] ModeSel[1] ModeSel[2] NC AUXPWR EESEL OSC/X1 X2 GNDA VCCA2 CONTROL VREF RTX GNDA VCC3A VCCA2 TP/FXIN TP/FXIP GNDA TP/FXON TP/FXOP GND VCC_Core LED_LNKACT LED_SPD LED_DUPCOL CONFIG1 CONFIG0 SCAN_EN RXD3 RXD2 GND VCC_Core RXD1 RXD0 RXDV RXCLK GND W89C841F/D W89C841F/D 4. PIN DESCRIPTION PCI Interface SIGNAL NAME PCICLK PIN TYP. I PIN NO. 117 PCI Clock Input A. Normal and MAC mode W89C841F supports PCI clock rate ranged from 25 MHz to 33 MHz continuously. All PCI signals except PCI_RSTB and INTAB are referenced on the rising edge of this clock. B. PHYceiver mode This pin should be pulled low. PCI_RSTB/ PHY_RSTB I 116 PCI Hardware Reset Signal (Normal and MAC mode) When asserted (active low), all PCI output pins of W89C841F will be in high impedance state, and all open drain signals will be floated. The configurations inside W89C841F will be in its initial state. This signal must be asserted for a period of at least 10 PCI clocks to correctly take effect of a reset on hardware. PHYceiver Reset (PHYceiver Mode) This pin is used as to reset PHYceiver. AD[31:12] IO/TS 123 - 127, 2 - 4, 7 - 9, 12 - 16, 29, 32 - 34 35 PCI Multiplexed Address[31:12] and Data Bus[31:12] During the first cycle that FRAMEB asserts, they act as an address bus; on the other cycles, they are switched to be a data bus. PCI Multiplexed Address[11] and Data Bus[11] (Normal and MAC mode) Power Down Enable (PHYceiver Mode) 1: Power Saving. 0: Normal. AD[10]/ INT IO/TS/ O 36 PCI Multiplexed Address[10] and Data Bus[10] (Normal and MAC mode) PHY Interrupt (PHYceiver Mode) Output low that is asserted to indicate an active interrupt event has occurred. DESCRIPTION AD[11]/ PWRDN IO/TS/ I -9- Publication Release Date: October 18, 2001 Revision A3 W89C841F/D PCI Interface, continued SIGNAL NAME AD[9:5]/ PHYA[4:0] PIN TYP. IO/TS/ I PIN NO. 37 - 38, 42 - 44 DESCRIPTION PCI Multiplexed Address[9:5] and Data Bus[9:5] (Normal and MAC mode) PHY Address (PHYceiver Mode) These pins indicate PHYceiver's address used for MII magement function AD[4]/ PAUREC IO/TS/ I 45 PCI Multiplexed Address[4] and Data Bus[4] (Normal and MAC mode) Pause Capability Recommend (PHYceiver Mode) This pin is recommended value for capability at full duplex operation. 1: With pause capability 0: No pause capability AD[3]/ XOVEN IO/TS/ I 46 PCI Multiplexed Address[3] and Data Bus[3] (Normal and MAC mode) Auto Cross Over Enable (PHYceiver Mode) In twist pair mode, this pin controls the function of cross over. 1: Enable 0: Disable AD[2]/ RECAN IO/TS/ I 47 PCI Multiplexed Address[2] and Data Bus[2] (Normal and MAC mode) Auto Negotiation Enable (PHYceiver Mode) 1: Enable 0: Disable AD[1]/ REC100 IO/TS/ I 48 PCI Multiplexed Address[1] and Data Bus[1] (Normal and MAC mode) Recommend 100M (PHYceiver Mode) 1: 100M 0: 10M AD[0]/ RECFUL IO/TS/ I 49 PCI Multiplexed Address[1] and Data Bus[1] (Normal and MAC mode) Recommend Duplex (PHYceiver Mode) 1: Full Duplex 0: Half Duplex - 10 - W89C841F/D PCI Interface, continued SIGNAL NAME C_BEB[3:0] PIN TYP. IO/TS PIN NO. 5, 17, 28, 39 DESCRIPTION Multiplexed Command and Byte Enables These signals are driven by current bus master. During address phase, they mean a bus command. On the other phase, they present the byte enable of the transaction. PAR IO/TS 27 Parity Signal This PAR represents the even parity across AD[31:0] and C_BEB[3:0]. It has the same timing as AD[31:0] but is delayed by one clock. FRAMEB IO/STS 18 PCI Cycle Frame The current bus master asserts FRAMEB to indicate the beginning and duration of a bus access. This signal keeps asserted while the current transaction is ongoing and keeps deasserted to indicate that the next data phase is the final data phase. IRDYB IO/STS 19 Initiator Ready The IRDYB is asserted by the current initiator to indicate the ability to complete the data transfer at the current data phase. The initiator asserts IRDYB to indicate the valid write data, or to indicate it is ready to accept the read data. More than or exactly one wait state will be inserted if IRDYB is deasserted during the current transaction. Data is transferred at the clock rising edge when both IRDYB and TRDYB are asserted at the same time. TRDYB IO/STS 22 Target Ready Asserted by the current target to indicate ability to complete data transfer at the current data phase. When W89C841F is operating at the bus slave mode, it asserts TRDYB to indicate that the valid read data presents on the bus or to indicate it is ready to accept data. Wait states will be inserted if TRDYB is deasserted. Data is transferred at the rising edge of the PCI clock when IRDYB and TRDYB are both asserted at the same time. STOPB IO/STS 24 PCI Stop Asserted by the current target to request PCI bus master to stop the current transaction. - 11 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D PCI Interface, continued SIGNAL NAME IDSEL PIN TYP. I PIN NO. 6 DESCRIPTION PCI Initialization Device Select A. Normal and MAC mode Asserted by host to signal the configuration access request to W89C841F. B. PHYceiver mode This pin should be pulled to low. DEVSELB IO/STS 23 PCI Device Select Asserted by the current target to indicate that it has finished decoding its address as the current access target. When W89C841F is the current master, it checks if the target asserted this signal within 5 PCI clocks after having issued command. If not, W89C841F will abort the access operation, releases PCI bus access right and acts no more bus master. When W89C841F is the target, it asserts DEVSELB in a medium speed, i.e., within 2 clocks. REQB O/TS 121 PCI Request Asserted by W89C841F to request bus ownership. REQB will be tri-stated when RSTB asserted. GNTB I/TS 120 PCI Grant A. Normal and MAC mode Asserted by host to grant that W89C841F have got the bus ownership. When RSTB asserted, W89C841F will ignore GNTB. B. PHYceiver mode This pin should be pulled to high. PERRB IO/STS 25 PCI Parity Error Asserted by the current data receiptor. When W89C841F acts the bus master, if a data parity error is detected and the parity error response bit (F04/FCS[6]) is also set, it will set both bits of F04/FCS[24] and C14/CISR[13] as 1 to terminate the current transaction after the current data phase is finished. When W89C841F acts the target, if a data parity error is detected and the bit F04/FCS[6] is set, it will assert PERRB only. - 12 - W89C841F/D PCI Interface, continued SIGNAL NAME SERRB PIN TYP. O/OD PIN NO. 26 System Error DESCRIPTION This pin is asserted with one PCI clock width within two PCI clocks after an address parity error is detected, and keeps in high impedance state when idle. The interrupt function caused by this event is gated by the bits in F04/FCS register. W89C841F will assert SERRB and will set a high to the Detect Parity Error bit F04/FCS[31] and the Signal System Erro bit F04/FCS[30] if an address parity error is detected and SERRB enable bit F04/FCS[8] is previously set to 1. The Bus Error Status bit C14/CISR[13] will be set to high if both an address parity error is detected and the parity error response bit F04/FCS[6] is set to high. INTAB O/OD 115 Interrupt A INTAB is asserted when any one of unmasked interrupt bits in C14/CISR is set. It keeps asserted until all of the unmasked interrupt bits is cleared. - 13 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Power Management Interface SIGNAL NAME STK_RSTB PIN TYP. I/PU PIN NO. 112 Sticky Reset Signal A. Normal and MAC mode Sticky_ResetB is a hardware reset signal which is generated from auxiliary power circuit if motherboard supports auxiliary power. So W89C841F can generate PMEB from D3(cold) state to D0 state transition and preserve PME context bits: PME_Status and PME_Enable. B. PHYceiver mode This pin should be floating. PWGD I 111 Power Good A. Normal and MAC mode When PWGD = 1, W89C841F is put in normal operation mode. When PWGD = 0, it isolates any PCI input and has all PCI outputs kept in high impedance state. The PCI bus power can be off by operating system. B. PHYceiver mode This pin should be pulled to high. PMEB O/OD 122 Power Management Event The PMEB signal indicates that a power management event has occurred, i.e. there is a magic packet received in suspend mode of host. CLKRUNB I/OD 113 Clock Run CLKRUNB is used to request starting or speeding up the PCI clock. It also indicates the PCI clock status. W89C841F requests the central resource to start, speed up, or maintain the PCICLK by the assertion of CLKRUNB. For the central resource, CLKRUNB is an S/T/S signal. The central resource is responsible for maintaining CLKRUNB asserted and for driving it high to deasserted state. DESCRIPTION - 14 - W89C841F/D Power Management Interface, continued SIGNAL NAME WOL/ CSTSCHG PIN TYP. O PIN NO. 114 DESCRIPTION Wake on LAN Signal The WOL signal indicates that a wake up event (Magic Packet, Link Status change and Wake-up frame) has been received. It is used to inform motherboard to execute wake-up process. The motherboard must support Wake-On-LAN. There are 4 types of output: active high (default), active low, positive pulse, negative pulse. CSTSCHG signal: This signal is used in CardBus application only and is used to inform motherboard to execute wake-up process whenever there is PMEB occurs. It is always an active high signal. BootROM/Flash and EEPROM Interface SIGNAL NAME BtAdd[17:14]/ RXD[3:0]_MAC/ RXD[3:0]_PHY PIN TYP. I/O/ I/ O PIN NO. 73, 72, 69, 68 PIN DESCRIPTION BootROM Address (Normal Mode) These pins are used as ROM address pins. MII Receive Data (MAC mode) These pins are used to input MII RXD signals. MII Receive Data (PHYceiver mode) These pins are used to output MII RXD signals. BtAdd[13]/ RXDV_MAC/ RXDV_PHY I/O/ I/ O 67 BootROM Address (Normal Mode) This pin is used as ROM address pin. MII Receive Data Valid (MAC mode) This pin is used to input MII RXDV signal. MII Receive Data Valid (PHYceiver mode) This pin is used to output MII RXDV signal. BtAdd[12]/ RXCLK_MAC/ RXCLK_PHY I/O/ I/ O 66 BootROM Address (Normal Mode) These pins are used as ROM address pin. MII Receive Clock (MAC mode) This pin is used to input MII RXCLK signal. MII Receive Clock (PHYceiver mode) This pin is used to output MII RXCLK signal. - 15 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D BootROM/Flash and EEPROM Interface, continued SIGNAL NAME BtAdd[11]/ RXER_MAC/ RXER_PHY PIN TYP. I/O/ I/ O PIN NO. 63 PIN DESCRIPTION BootROM Address (Normal Mode) These pins are used as ROM address pin. MII Receive Error (MAC mode) This pin is used to input MII RXER signal. MII Receive Error (PHYceiver mode) This pin is used to output MII RXER signal. BtAdd[10]/ TXER_MAC/ TXER_PHY I/O/ O/ I 62 BootROM Address (Normal Mode) These pins are used as ROM address pin. MII Transmit Error (MAC mode) This pin is used to output MII TXER signal. MII Transmit Error (PHYceiver mode) This pin is used to input MII TXER signal. BtAdd[9]/ TXCLK_MAC/ TXCLK_PHY I/O/ I/ O 61 BootROM Address (Normal Mode) These pins are used as ROM address pin. MII Transmit Clock (MAC mode) This pin is used to input MII TXCLK signal. MII Transmit Error (PHYceiver mode) This pin is used to output MII TXCLK signal. BtAdd[8]/ TXEN_MAC/ TXEN_PHY I/O/ O/ I 60 BootROM Address (Normal Mode) These pins are used as ROM address pin. MII Transmit Enable (MAC mode) This pin is used to output MII TXEN signal. MII Transmit Enable (PHYceiver mode) This pin is used to input MII TXEN signal. BtAdd[7:4]/ TXD[3:0]_MAC/ TXD[3:0]_PHY I/O/ O/ I 59, 58, 57, 56 BootROM Address (Normal Mode) These pins are used as ROM address pins. MII Transmit Data (MAC mode) These pins are used to output MII TXD signals. MII Transmit Data (PHYceiver mode) These pins are used to input MII TXD signals. - 16 - W89C841F/D BootROM/Flash and EEPROM Interface, continued SIGNAL NAME BtAdd[3]/ COL_MAC/ COL_PHY PIN TYP. I/O/ I/ O PIN NO. 55 PIN DESCRIPTION BootROM Address (Normal Mode) This pin is used as ROM address pin. MII Collision (MAC mode) This pin is used to input MII COL signal. MII Collision (PHYceiver mode) This pin is used to output MII COL signal. BtAdd[2]/ CRS_MAC/ CRS_PHY I/O/ I/ O 54 BootROM Address (Normal Mode) This pin is used as ROM address pin. MII Carrier Sense (MAC mode) This pin is used to input MII CRS signal. MII Carrier Sense (PHYceiver mode) This pin is used to output MII CRS signal. BtAdd[1]/ MDIO_MAC/ MDIO_PHY I/O 53 BootROM Address (Normal Mode) This pin is used as ROM address pin. MII Management Data (MAC mode) This pin is used to input/output MII MDIO signal. MII Management Data (PHYceiver mode) This pin is used to input/output MII MDIO signal. BtAdd[0]/ MDC_MAC/ MDC_PHY I/O/ O/ I 52 BootROM Address (Normal Mode) These pins are used as ROM address pin. MII Management Clock (MAC mode) This pin is used to output MII MDC signal. MII Management Clock (PHYceiver mode) This pin is used to input MII MDC signal. BtData[7:5]/ ModeSel[2:0] I/O 100 - 102 BootROM Data[7:5] These pins are used as ROM data pins. Mode Selection When power-on, these pins are used as input pins to latch the setting value of ModeSel. Mode Normal MAC Controller PHYceiver Testing CONFIG 00 01 10 11 ModeSel 000 011 000 xxx - 17 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D BootROM/Flash and EEPROM Interface, continued SIGNAL NAME BtData[4] PIN TYP. I/O PIN NO. 103 A. Normal mode PIN DESCRIPTION BootROM Data[4] This pin is used as ROM data pin. B. PHYceiver mode and MAC mode This pin should be pulled to low. BtData[3]/ SELFX I/O/ I 104 BootROM Data[3] This pin is used as ROM data pin FX/TX Selection When power-on, this pin is used as input pin to latch the setting value of SELFX. 1: FX mode 0: TX mode BtData[2]/ EEDO/ PHY_Duplex I/O/ O 105 BootROM Data[2]/ EEPROM Data Output (Normal mode and MAC mode) This is pin is used for BootROM data pin or EEPROM data output dependent on the bit EESEL of register Dc4/DEEAR. PHY_DUPLEX (PHYceiver mode) This pin output the PHYceiver duplex status. 1: Half Duplex 0: Full Duplex BtData[1]/ EEDI I/O 106 BootROM Data[1]/ EEPROM Data Input This is pin is used for BootROM data signal or EEPROM data input dependent on the bit EESEL of register Dc4/DEEAR. BtData[0]/ EECK I/O 107 BootROM Data[0]/ EEPROM Data Clock This is pin is used for BootROM data signal or EEPROM data clock dependent on the bit EESEL of register Dc4/DEEAR. EECS BtCSB O O 108 99 EEPROM Chip Select BootROM Chip Select - 18 - W89C841F/D BootROM/Flash and EEPROM Interface, continued SIGNAL NAME BtOEB/ AuxPWR PIN TYP. I/O PIN NO. 98 PIN DESCRIPTION BootROM Read Enable/ Auxiliary Power Detection A. Normal mode and MAC mode After power on latch, auxiliary power is automatically detected by W89C841F. If auxiliary power is detected to be high, wake-up event generation from D3(cold) to D0 (uninitialized) state is supported. B. PHYceiver mode This pin should be pulled to low. BtWEB/ EESel I/O 97 BootROM Write Enable/ EEPROM Type Select A. Normal mode and MAC mode After power on latch, EEPROM type is detected by W89C841F. If it is high, EEPROM (93C56) is used for CardBus application. Otherwise, EEPROM (93C46) is used in PCI/Mini PCI application. B. PHYceiver mode This pin should be pulled to low. Transceiver Interface SIGNAL NAME TP/FXOP TP/FXON TP/FXIP TP/FXIN OSC/X1 X2 PIN TYP. O O I I I O PIN NO. 82 83 85 86 96 95 PIN DESCRIPTION Twist Pair / Fiber Transmit Output Positive Twist Pair / Fiber Transmit Output Negative Twist Pair / Fiber Receive input Positive Twist Pair / Fiber Receive input Negative 25 MHz Crystal/OSC clock input Crystal Output Left unconnected when oscillator is chosen for X1 input. VREF RTX CONTROL I I O 91 90 92 RC input for Bias. RC input for Transmitter. 2.5V Regulator Control Output Drive current below 10 mA. - 19 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D LED Interface SIGNAL NAME LED_ LNKACT LED_SPD I/O 78 PIN TYP. I/O PIN NO. 79 LED_LNKACT 0: Link up without activity. 1: Link fail or activity is on (flash 100 mS) LED_SPD 0: 100M. 1: 10M. LED_ DUPCOL I/O 77 LED_DUPCOL 0: Full duplex or collision in half duplex (flash 100 mS) 1: Half duplex and no collision. PIN DESCRIPTION Configuration and Test Interface SIGNAL NAME CONFIG[1:0] PIN TYP. I PIN NO. 76, 75 Configuration 00: Normal mode 01: MAC controller mode (Disable internal PHYceiver and disable Boot ROM function) 10: PHYceiver mode (Disable MAC Controller and Boot ROM function) 11: Reserved for testing Scan_EN I 74 Scan Enable Reserved for testing. This pin should be pulled to low. PIN DESCRIPTION Power Pins SIGNAL NAME VCCA2 VCC3A GNDA VCC VCC_Core GND PIN TYP. PIN NO. 87, 93 88 84, 89, 94 10, 20, 30, 40, 64, 109, 128 50, 70, 80, 119 1, 11, 21, 31, 41, 51, 65, 71, 81, 110, 118 PIN DESCRIPTION 2.5V Analog Power 3.3V Analog Power Analog Ground 3.3V I/O Digital Power 2.5V Core Digital Power Digital Ground - 20 - W89C841F/D Pins Mapping Table W89C841F can be configured into 3 different operational types. In the following table, it lists the pin mapping of different configuration mode. NORMAL MODE Config = 00 ModeSel [2:0] = 000 LED_LNKACT LED_SPD LED_DUPCOL BTADD17 BTADD16 BTADD15 BTADD14 BTADD13 BTADD12 BTADD11 BTADD10 BTADD9 BTADD8 BTADD7 BTADD6 BTADD5 BTADD4 BTADD3 BTADD2 BTADD1 BTADD0 BTDATA7 BTDATA6 BTDATA5 BTDATA4 MAC CONTROLLER MODE Config = 01 ModeSel [2:0] = 011 LINK (I) SPEED (I) DUPLEX (I) RXD3 (I) RXD2 (I) RDX1 (I) RDX0 (I) RXDV (I) RXCLK (I) RXER (I) TXER (O) TXCLK (I) TXEN (O) TXD0 (O) TXD1 (O) TXD2 (O) TXD3 (O) COL (I) CRS (I) MDIO (I/O) MDC (O) ModeSel[2] ModeSel[1] ModeSel[0] NC PHYCEIVER MODE Config = 10 ModeSel [2:0] = 000 LED_LNKACT (O) LED_SPD (O) LED_DUPCOL (O) RXD3 (O) RXD2 (O) RDX1 (O) RDX0 (O) RXDV (O) RXCLK (O) RXER (O) TXER (O) TXCLK (O) TXEN (I) TXD0 (I) TXD1 (I) TXD2 (I) TXD3 (I) COL (O) CRS (O) MDIO (I/O) MDC (I) ModeSel[2] ModeSel[1] ModeSel[0] NC - 21 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Pins Mapping Table, continued NORMAL MODE Config = 00 ModeSel [2:0] = 000 BTDATA3 BTDATA2/ EEDO BTDATA1/ EEDI BTDATA0/ EECLK BTCSB BTOEB BTWEB AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 MAC CONTROLLER MODE Config = 01 ModeSel [2:0] = 011 NC EEDO EEDI EECLK NC NC NC AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PHYCEIVER MODE Config = 10 ModeSel [2:0] = 000 SELFX PHY_DPULEX NC NC NC NC NC PWRDN (I) INT (O) PHYA[4] (I) PHYA[3] (I) PHYA[2] (I) PHYA[1] (I) PHYA[0] (I) PAUREC (I) XOVEN (I) RECAN (I) REC100 (I) RECFUL (I) - 22 - W89C841F/D 5. BLOCK DIAGRAM PCI long word aligning buffer PCI interface data driver TX FIFO RX FIFO MII data buffer XCVR MII Media receive data DMA machine PCI bus master transmit data DMA machine control signals Media Access Controller memory interface PCI bus slave controller control registers Expansion ROM interface EEPROM access interface configuration registers status registers Figure 2. W89C841F Block Diagram - 23 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D 6. SYSTEM DIAGRAM * NIC product: PCI LAN card, Card bus LAN card, MiniPCI LAN card 25 MHz LED EEPROM P C I I/f Magnetic W89C841F Boot ROM/Flash RJ45 Figure 3. NIC Application * Home Networking product: HomePNA MAC W89C841F MII Home PNA Figure 4. HomePNA Application * LAN On Mother board: LOM PHY MAC MII W89C841F Chipset Figure 5. LOM Application - 24 - W89C841F/D * PCI application: Restore card, Firewall, Education system EEPROM W89C841F Flash (Application S/W) PCI i/f Figure 6. Restore Card Application 7. FUNCTIONAL DESCRIPTION Operation Mode Configuration W89C841F can be configured to 3 different operation modes for different applications. In the following table, the assignment of pins CONFIG[1:0] and ModeSel[2:0] is listed. PIN ASSIGNMENT CONFIG[1:0] Mode_Sel[2:0] NORMAL 00 000 MAC CONTROLLER 01 011 PHYCEIVER 10 000 In the normal mode, W89C841F is used in the NIC application. In the MAC controller mode, W89C841F that is used as a MAC controller plus HomePHY that is used as a transceiver implement a HomePNA card. In the PHYceiver mode, an application like LAN On Motherboard (LOM) is implemented by W89C841F that is used as a single PHYceiver plus PC chipset. PHYceiver An internal PHYceiver is embedded in W89C841F. It is compatible with IEEE802.3 10-BAST-T, 100BASE-TX and 100BAST-FX. W89C841F can be configured to twist pair interface or fiber interface. Auto-negotiation and auto-crossover function is supported. W89C841F provides 3 LEDs to indicate Link/Activity, Speed and Duplex/Collision status. Direct Memory Access Function On receiving a data packet, the receive DMA function will transfer these data from the internal receive FIFO which has a size of 2k bytes to the host memory with the assistance of the on-chip PCI bus master. During the transaction cycle, the media access controller (MAC) requests the receive DMA state machine to move the data in the receive FIFO onto the PCI bus, and then move it to the host memory. - 25 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D W89C840F transmit DMA function performs the data transfer from the host memory through on-chip PCI bus master into the internal 2 Kbytes transmit FIFO. The transmit DMA state machine will request the MAC to send out the data in the TX FIFO onto the transmission media. Media Access Control (MAC) Function The MAC function of W89C841F fully meets the requirements defined by the IEEE802.3u specification. MAC performs many transmission functions, including the inter-frame spacing function, collision detection, collision enforcement, collision backoff and retransmission. MAC performs the receive functions including the address recognition function, the frame check sequence validation, the frame disassembly, framing and collision filtering. Full Duplex and Half Duplex Function In the half duplex mode, the MAC should perform the transmission or reception operation at the different time frame. Simultaneous transmission and reception is not allowed. However, in the time duration from 10 bits time to 16 bits time after the packet is transmitted, the active COL signal is recognized as a SQE test signal but not a collision event. The active signal CRS will be recognized as a loopback carrier sense signal when the MAC is transmitting a packet. The carrier sense lost status is relied on the CRS. Normally, there should not be any carrier sense lost during transmitting if the media and devices are functional. In the full duplex mode, the MAC can perform the transmission and receive operation at the same time. Collision event, SQE lost and carrier sense lost are not defined in the full duplex mode. After auto-negotiation completed, network duplex mode can be decided by internal PHYceiver. Network Media Speed Function W89C841F can work at network speed of 100M or 10Mbps. After auto-negotiation completed, network speed can be decided by internal PHYceiver. Flow Control in Full Duplex Mode W89C841F supports asymmetrical and symmetrical flow control in full duplex mode compliant with IEEE802.3x. After auto-negotiation completed, W89C841F will decide to operate in which flow control mode (symmetrical, asymmetrical or none). When the receiving byte counts of RX FIFO is over the high threshold defined at field HTV of register Ddc/DRFCTV[17:9], a pause frame with MAX pause time (FFFFh) is transmitted to prevent the other station keeping on transmitting packets to W89C841F. So W89C841F will not drop packets due to RX FIFO overflow. When the receiving byte count of RX FIFO is below the low threshold defined at field LTV of register Ddc/DRFCTV[8:0], a pause frame with MIN pause time (0000h) is transmitted to let the other station starting to transmit packets to W89C841F. If W89C841F receives a pause packet with non-zero pause time, the packet transmission ability will be inhibited until the pause time counts down to 0. Pause frame is a flow control packet. It is not a data packet and will be dropped by W89C841F. Priority Tagged Frame Supporting QOS A priority tagged frame defined at IEEE 802.1p contains a VLAN tag which indicates the user priority and Null VLAN ID (VID = 0). W89C841F can transmit and receive priority tagged frames to improve the network quality of service if bit VLANEN of register C1c/CNCR is set. - 26 - W89C841F/D EEPROM Auto-load and Software Programming Function W89C841F reads configuration parameter from EEPROM and stores these data into the configuration registers and function registers after hardware reset. EEPROM 93C46 or 93C56 will be the choice as the storage device for storing these data according to different application. In PCI/Mini-PCI application, W89C841F stores configuration parameters and Vital Product Data (VPD) in EEPROM 93C46. Configuration parameters and relative register are listed below: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18) 19) 20) 21) 22) 23) 6 bytes Ethernet address 1 byte maximum latency 1 byte minimum grant 2 bytes subsystem ID (Register Dcc[31:0] and Dd0[15:0]) (Register F3c[31:24]) (Register F3c[23:16]) (Register F2c[31:16]) (Register F2c[15:0]) 2 bytes subsystem Vendor ID 2 bytes Device ID 2 bytes Vendor ID (Register F00[31:16]) (Register F00[15:0]) (Register F28[31:0]) 4 bytes CardBus CIS Pointer 1 bit Power Management Data Enable 3 bits Auxiliary Current 2 bits Data Scale (Register Fdc[24:22]) (Register Fe0[14:13]) 6 bytes Power Consumption and Dissipation data for D0, D1 and D3 State (Register Fe0[31:24]) 1 bits Power Management Enable 1 bit VPD Enable 2 bits Bus Type (Register D00[6]) (Register D00[5]) (Register D00[1:0]) (Register D00[11]) 1 bit CLKRUN enable 1 bit Magic Packet enable (Register D00[10]) 3 bits Boot ROM Size (Register Dc0[30:28]) 1 byte Base Class Code (Register F08[31:24]) 1 byte Subclass code (Register F08[23:16]) 1 byte Interface Code (Register F08[15:8] 1 bytes Revision ID 64 Bytes VPD Data (Register F08[7:0] - 27 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D EEPROM 93C46 ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh HIGH BYTE (Bit 15 - Bit 8) Ethernet Address 1 [15:8] Ethernet Address 3 [31:24] Ethernet Address 5 [47:40] MAXLAT Subsystem ID (high byte) Subsystem Vendor ID (high byte) Device ID (high byte) Vendor ID (high byte) CardBus CIS pointer (Low Word) CardBus CIS pointer (High Word) PM_Data_En {bit15} Aux_Current {bit15 - bit13} D0 Power Consumption Data D1 Power Consumption Data D3 Power Consumption Data PM_EN {bit15} VPD_EN {bit14} PCBusType {bit13 - bit12} CKRUN_EN {bit11} MAGP_EN {bit10} 10h 11h 12 - 1Fh 20h - 3Fh Base Class Code Interface Code Reserved Vital Product Data (VPD) Subclass code Revision ID Reserved Reserved Data_Scale {bit7 - bit6} D0 Power Dissipation Data D1 Power Dissipation Data D3 Power Dissipation Data Boot ROM Size {bit7 - bit5} LOW BYTE (Bit 7 - Bit 0) Ethernet Address 0 [7:0] Ethernet Address 2 [23:16] Ethernet Address 4 [39:32] MINGNT Subsystem ID (Low byte) Subsystem Vendor ID (low byte) Device ID (low byte) Vendor ID (low byte) In CardBus application, another data structure of CardBus Information Structure (CIS) needs to be stored in the EEPROM 93C56. Totally 128 bytes space addressed from 40h to 7Fh are reserved for CIS use. - 28 - W89C841F/D EEPROM 93C56 ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh HIGH BYTE (Bit 15 - Bit 8) Ethernet Address 1 [15:8] Ethernet Address 3 [31:24] Ethernet Address 5 [47:40] MAXLAT Subsystem ID (high byte) Subsystem Vendor ID (high byte) Device ID (high byte) Vendor ID (high byte) CardBus CIS pointer (Low Word) CardBus CIS pointer (High Word) PM_Data_En {bit15} Aux_Current {bit15 - bit13} D0 Power Consumption Data D1 Power Consumption Data D3 Power Consumption Data PM_EN {bit15} VPD_EN {bit14} PCBusType {bit13 - bit12} CLKRUN_EN {bit11} MAGP_EN {bit10} 10h 11h 12h - 1Fh 20h - 3Fh 40h - 7Fh Base Class Code Interface Code Reserved Vital Product Data (VPD) CardBus Information Structure Subclass code Revision ID Reserved Reserved Data_Scale {bit7-bit6} D0 Power Dissipation Data D1 Power Dissipation Data D3 Power Dissipation Data Boot ROM Size {bit7- bit5} LOW BYTE (Bit 7 - Bit 0) Ethernet Address 0 [7:0] Ethernet Address 2 [23:16] Ethernet Address 4 [39:32] MINGNT Subsystem ID (Low byte) Subsystem Vendor ID (low byte) Device ID (low byte) Vendor ID (low byte) - 29 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Dc4/DEEAR register is used as an interface to access the data between the system and EEPROM. The following table lists the reading and writing steps for EEPROM. COMMAND EEPROM Read STEP Set EEPROM access bit EESEL to 1. Set EEPROM offset address to bits EEOA Set EEPROM Read command to bit EERW Set Start EEPROM Read/write command to bit StartEERW Waiting for read operation completed until bit StartEERW change to 0. Read data from bits EEData. Disable EEPROM Write Protection Set EEPROM access bit EESEL to 1. Set EEPROM write protection disable command to bit EERW Set Start EEPROM Read/write command to bit StartEERW Waiting for write protection disable operation completed until bit StartEERW change to 0. EEPROM Write 1) Set EEPROM access bit EESEL to 1. 2) Set EEPROM offset address to bits EEOA 3) Set EEPROM Data to bits EEData 4) Set EEPROM write command to bit EERW 5) Set Start EEPROM Read/write command to bit StartEERW 6) Waiting for write operation completed until bit StartEERW change to 0. Enable EEPROM Write Protection Set EEPROM access bit EESEL to 1. Set EEPROM write protection enable command to bit EERW Set Star EEPROM Read/Write command to bit StartEERW. Waiting for bit StartEERW change to 0. BootROM Read and Flash Programming Function W89C841F can address up to 256 Kbytes memory space for the on-board BootROM or Flash memory device. The on-board BootROM device will be mapped into the host memory by the system BIOS. W89C841F will return the mapped memory address depending on the field BootROM size select of register Dc0/DBRAR[30:28]. This field is loaded from EEPROM after power on reset. The relationship between the return value from the register F30/FERBA and the field BootROM size select of register Dc0/DBRAR[30:28] is listed as the following table. - 30 - W89C841F/D ROM SIZE None None 8 Kbytes 16Kbytes 32Kbytes 64Kbytes 128Kbytes 256Kbytes DC0/DBRAR[30:28] 000b 001b 010b 011b 100b 101b 110b 111b F30/FERBA 0000_0000h 0000_0000h FFFF_E001h FFFF_C001h FFFF_8001h FFFF_0001h FFFE_0001h FFFC_0001h The address decoder of W89C841F for accessing the on-board BootROM will be enabled if both the bit 0 of F30/FERBA and the bit 1 of F04/FCS are set to high at the same time. On-board Boot ROM data will be fetched by W89C841F and are loaded into the host memory. On the other hand, the address decoder will be disabled if the bit 0 of F30/FERBA is reset to 0. Under this case, W89C841F will ignore the Dc0/DBRAR, no matter what content it has. Usually on-board BootROM data can be read by the system BIOS during host system booting or power-on reset. W89C841F also provides an access method by register Dc0/DBRAR and Dc0/DEEAR[31] to read or write Flash memory on Restore Card applications. If BootROM interface is chosen to be accessed, the bit EESEL of register Dc4/DEEAR[31] must be set to 0 at first. The read and write process for BootROM or Flash through register Dc0/DBRAR is listed in the following table. COMMAND Read STEP 1) Set BootROM access bit EESEL (Dc4/DEEAR[31]) to 0. 2) Set the BootROM/Flash offset address to bits BROMA 3) Set BootROM/Flash read control bit BROMRD to 1. 4) Waiting for read operation completed until bit BROMRD change to 0. 5) Read back the data from bits BROMD Write 1) Set BootROM access bit EESEL (Dc4/DEEAR[31]) to 0. 2) Set the Boot ROM offset address to bits BROMA 3) Write data to bits BROMD 4) Set BootROM write control bit BROMWR to 1. 5) Waiting for write operation completed until bit BROMWR change to 0. - 31 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D The bit BROMRD (bit 27) and bit BROMWR (bit 26) of the register Dc0/DBRAR should not be set to 1 at the same time. In the case of both of the bit BROMRD and bit BROMWR are 1, it will not properly initialize the read or the write operation for ROM device. The application program can check the contents of the register Dc0/DBRAR to know if the read or write operation is already completed or not. W89C841F will start the read or the write operation when the bit BROMRD or bit BROMWR are set to high and will be reset automatically after the read/write operation is completed. For the write operation, the software driver should not start up the next write data request until the bit BROMWR of Dc0/DBRAR[26] is reset to 0 by W89C841F. For the read operation, the read data will be valid only if the bit BROMRD of the register Dc0/DBRAR[27] is reset to 0 by W89C841F. MII Management Function W89C841F supports MII management function through register Dc8/DMMAR to access the MII management registers of the internal PHYceiver (Normal mode) or external PHYceiver (MAC controller mode). The following table lists the read and write access steps for MII management registers. COMMAND Read STEP Set PHY address to bits PHYADD to default value 01h. Set PHY register address to bits REGADD Set MDIO read command to bit MDIORW Set Start MDIO Read/write command to bit StartMDIORW Waiting for read operation completed until bit StartMDIORW change to 0. Read data from bits PHYData. Write Set PHY address to bits PHYADD to default value 01h Set PHY register address to bits REGADD Set PHY data to bits PHYData Set MDIO write command to bit MDIORW Set Start MDIO Read/write command to bit StartMDIORW 6) Waiting for write operation completed until bit StartMDIORW change to 0. System Resource Configuring W89C841F will require the I/O space, memory space for function Cxx and Dxx registers and the interrupt line to perform the communication between the network and the host. In PCI/MiniPCI system, Cxx and Dxx registers can be mapped to either system I/O space or memory space. The following table lists the relative mapping address in double word aligned. I/O SPACE ADDRESS Cxx Registers Dxx Registers 00h - 3Ch 00h - FFh MEMORY SPACE ADDRESS 000h - 03Ch 100h - 1FCh - 32 - W89C841F/D In CardBus system, Cxx and Dxx registers can be mapped to either system I/O space or memory space. But CIS data can be mapped to memory space only. The following table lists the relative mapping address in double word. I/O SPACE ADDRESS Cxx Register CIS Data Dxx Register 00h - 3Ch X 00h - FFh MEMORY SPACE ADDRESS 000h - 03Ch 080h - 0FCh 100h - 1FCh W89C841F uses only one interrupt pin INTAB. However, the interrupt line resource assignment is determined by the system BIOS by writing the related data into the bits ILINE of register F3C/FIR[7:0]. Power Management Function W89C841F supports power management function that is compliant with ACPI R1.0, PCI power management R1.1 and Network Device Class Power management Reference specification V1.0a. Power management state from D0, D1, D3(hot) is provided by W89C841F. But whether the D3(cold) power management state is provided is dependent on the auxiliary power detected or not after power on reset. Power management D2 is not supported by W89C841F. PME context consists of the bit PME_EN of register Fe0/FPMR1[8] and bit PME_STS of register Fe0/FPMR1[15]. If D3(cold) power management state is supported, PME context will be kept valid. When PMEB is asserted, it must continue to drive the signal low until software explicitly either clears the PME Status bit or clears the PME Enable bit. Wake-On-LAN Function If the power management function is enabled, 3 types of wake-up events can be accepted by W89c841F to acknowledge driver that wake-up event has happened. These wake-up events are defined as: * Link status changed * Magic Packet * Wake-up frame 8. CONFIGURATION REGISTERS The general attributes of the PCI configuration registers implemented in W89C841F are described as the following. 1) Writes to the reserved configuration registers are treated as no-op. The bus access will complete without affecting any data in W89C841F internal registers. 2) Read from the reserved or un-implemented registers will be returned 0 value. 3) SoftReset has no effect on the PCI configuration registers. 4) HardReset will clear the PCI configuration registers. 5) The implemented configuration registers support any byte enable combination access. - 33 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D 6) Burst access to the configuration registers will be terminated after 1st data transfer completed with a disconnect without data. The following table outlined all the PCI configuration registers inside this chip and summarized its function. Configuration Register Mapping CODE F00 F04 F08 F0c F10 F14 F18 ---F28 F2c F30 F34 ---F3c F40 Fdc Fe0 Fe4 Fe8 ABBREVIATION FID FCS FREV FLT FBIOAC FBIOAD FBMA ----FCISPR FSSID FERBA FCAPR ----FIR FSR FPMR0 FPMR1 FVPDR0 FVPDR1 Identification Command and status Revision Latency timer Base I/O address for Cxx registers Base I/O address for Dxx registers Base memory address Reserved CardBus CIS pointer Subsystem ID Expansion ROM base address Capabilities pointer Reserved Interrupt Signature Power Management Register 0 Power management Register 1 Vital Product Data Register 0 Vital Product Data Register 1 MEANING SYSTEM I/O OFFSET 00h 04h 08h 0ch 10h 14h 18h 1ch - 24h 28h 2Ch 30h 34h 38h 3Ch 40h DCh E0h E4h E8h - 34 - W89C841F/D This table lists the initial state of each register in W89C841F after Stk_ResetB, PCI_ResetB, D3toD0_ResetB and software reset. CODE F00 F04 F08 F0c F10 F14 F18 F28 F2c F30 F34 F3c F40 Fdc Fe0 Fe4 Fe8 ABBR. FID FCS FREV FLT FBIOAC FBIOAD FBMA FCISPR FSSID FERBA FCAPR FIR FSR FPMR0 FPMR1 FVPDR0 FVPDR1 STK_RESETB, PCI_RESETB D3TOD0_RESETB 0000_0000h 0280_0000h 0200_0000h 0000_0000h FFFF_FFC1h FFFF_FF01h FFFF_FE00h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0100h 0000_0044h 5A02_0001h 0000_0100h 0000_0003h 0000_0000h Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected SOFTWARE RESET F00/FID Device ID Register The register specifies the vendor ID and the device ID. BIT 31:16 15:0 ATTRIBUTE R R BIT NAME DID VID Device ID Loaded from EEPROM after hardware reset. Vendor ID Loaded from EEPROM after hardware reset. FFFFh is an invalid value for vendor ID. DESCRIPTION - 35 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D F04/FCS Command and Status Register The F04/FCS comprises two parts, one is the command register (FCS[15:0]) which provides the control of PCI activity, and another is the status register (FCS[31:16]) which shows the status information of PCI event. Writing 1 to the bits of the status register will clear them; writing 0 has no effect. BIT 31 ATTRIBUTE R/WC BIT NAME DPE Detected Parity Error The DPE bit will be set if a parity error is detected by W89C841F even the parity error response bit of register F04/FCS[6] is disabled. 30 29 R/WC R/WC SSE RMA Signaled System Error The SSE bit will be set if W89C841F assert SERRB. Received Master Abort The RMA bit will be set if W89C841F master transaction is terminated by a master abort. 28 R/WC RTA Received Target Abort The RTA bit will be set if W89C841F master transaction is terminated by a target abort. 27 R/WC STA Signaled Target Abort The STA bit will be set if W89C841F slave transaction takes a target abort. 26:25 24 R R/WC DT MDPE DEVSELB Timing Fixed at 01b. Indicate a medium DEVSEL# assert timing. Master Data Parity Error The MDPE bit will be set if the following three conditions are met: 1). W89C841F asserts PERRB (on a read) or observes PERRB asserted (on a write). 2). W89C841F acts as a master in the transaction that the error occurs. 3). The parity error response bit of register F04/FCS[6] is set. DESCRIPTION - 36 - W89C841F/D F04/FCS Command and Status Register, continued BIT 23 ATTRIBUTE R BIT NAME FBTBC DESCRIPTION Fast Back-to-Back Capable Fixed at 1. Indicates the capability of accepting fast back to back transactions which are not accessing to the same target. 22:21 20 R R --CAPS Reserved. Fixed at 0. Capabilities List The value is dependent on the PMEn and VPDEn loaded from EEPROM to decide the W89C841F power management and Vital Product Data capability. While CAPS is equal to 1: indicates that W89C841F supports the PCI Power Management and/or VPD. 0: indicates that W89C841F does not support Power Management and VPD. 19:9 8 R R/W --SE Reserved. Fixed at 0. SERRB Enable Set SE bit high to enable W89C841F to assert SERRB if an address parity error is detected. This bit and bit PER must be set 1 to signal SERR event. 7 6 R R/W ---PER Reserved. Fixed at 0. Parity Error Response Set PER bit to high to enable the W89C841F to respond to parity error. When PER is reset, W89C841F will ignore any parity error and continue the normal operation. W89C841F internal parity checking and generation function will not be disabled even PER is reset. 5:3 2 R R/W --BM Reserved. Fixed at 0. Bus Master Set BM bit to high will allow W89C841F acting as a bus master. Reset BM bit to low will disable the W89C841F bus master ability. 1 R/W MS Memory Space Set MS bit to high will allow W89C841F to respond to memory space access by the host. 0 R/W IOS I/O Space Set IOS bit to high will allow W89C841F to respond to I/O space access by the host. - 37 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D F08/FREV Device Revision Register This register which is read-only shows class code, subclass code, interface code and revision ID. BIT 31:24 23:16 15:8 7:0 ATTRIBUTE R R R R BIT NAME BC SC IC REV Base Class Code Loaded from EEPROM. Subclass Code Loaded from EEPROM. Interface Code Loaded from EEPROM. Revision ID Loaded from EEPROM. DESCRIPTION F0C/FLT Latency Timer Register This register specifies the latency timer of master bus in units of PCI bus clock. BIT 31:24 23:16 15:8 ATTRIBUTE R R R/W BIT NAME --HT LT DESCRIPTION Reserved, Fixed to 0. Header Type, Fixed to 0. Latency Timer Specify, in units of PCI clocks, the latency timer value of W89C841F. When W89C841F asserts FRAMEB, its latency timer starts counting up. W89C841F will initiate the transaction termination as soon as its GNTB de-asserted if the timer expired before W89C841F de-asserts FRAMEB. Reserved. Fixed at 0. 7:0 R --- F10/FBIOAC Base I/O Address for Cxx Function Registers This register is written by software after power-on reset to specify W89C841F base I/O address for Cxx function registers access in the system. BIT 31: 6 ATTRIBUTE R/W BIT NAME BIOA DESCRIPTION Base I/O Address Written by power-on software to specify base I/O address for Cxx function registers. W89C841F requires a 64 bytes I/O space. Reserved. Fixed at 0. I/O Space Indicator Fixed at 1. 5:1 0 R R --IO - 38 - W89C841F/D F14/FBIOAD Base I/O Address for Dxx Function Registers This register is written by software after power-on reset to specify W89C841F base I/O address for Dxx function registers in the system. BIT 31: 8 ATTRIBUTE R/W BIT NAME BIOA Base I/O Address Written by power-on software to specify base I/O address for Dxx function registers. W89C841F requires a 256 bytes I/O space. 7:1 0 R R --IO Reserved. Fixed at 0. I/O Space Indicator Fixed at 1. DESCRIPTION F18/FBMA Base Memory Address Register This register is written by power-on software to specify W89C841F base memory address in the system. BIT 31: 9 ATTRIBUTE R/W BIT NAME BMA DESCRIPTION Base Memory Address Written by power-on software to specify base memory address for both of Cxx and Dxx function registers. W89C841F requires a 512 bytes memory space. 8:1 0 R R --MEM Reserved. Fixed at 0. Memory Space Indicator Fixed at 0. - 39 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D F28/FCISPR CardBus CIS Pointer Register This register identifies the location of the Card Information Structure (CIS). In W89C841F, CIS data can be stored in EEPROM or BootROM. CIS pointer value is loaded from EEPROM. BIT 31:28 ATTRIBUTE R BIT NAME RIN ROM Image Number This field defines the ROM image number (0-Fh) in which the CIS is located. The offset value is added to the start of the ROM image to identify the start of the CIS. 27:3 R ASO Address Space Offset This field defines which space the CIS resides within. Memory space: This is the offset into the memory address space governed by Base Address Register F18/FMBA. Adding this value to the value in the Base Address Register gives the location of the start address of the CIS. Bits ASO is fixed to 80h. Expansion ROM space: The offset value is from the start of the ROM image identified by bits RIN. 2:0 R ASI Address Space Indicator Specifies the base address within the space indicated. The offset bits ASO is added to this base address to identify the start of the CIS. The address indicators values are: 3 = CIS is in the memory pointed to by the base address register 2. 7 = CIS is in the Boot ROM. Bits RIN identify which Boot ROM image. Other values are reserved. DESCRIPTION F2C/FSSID Subsystem ID Register This register stores the Subsystem ID and Subsystem Vendor ID. BIT 31:16 15:0 ATTRIBUTE R R BIT NAME SBID SBVID Subsystem ID Loaded from EEPROM. Subsystem Vendor ID Loaded from EEPROM. DESCRIPTION - 40 - W89C841F/D F30/FERBA Expansion ROM Base Address Register This register is written by power-on software to specify the on-board Boot ROM base address in the system. BIT 31:13 ATTRIBUTE R/W BIT NAME EROMB DESCRIPTION Expansion ROM Base Address Written by power-on software to specify expansion ROM base address. W89C841F will request up to 256K bytes memory space for the on board Boot ROM according the configuration of bit BROMSEL of register Dc0/DBRAR[30:28]. 12:1 0 R R/W --ROME Reserved. Fixed at 0. Expansion ROM Enable Set both of this bit and memory space bit of register F04/FCS[1] to 1 to enable expansion ROM access ability. F34/FCAPPR Capabilities Pointer Register W89C841F has the capabilities of Power Management and/or Vital Product Data. This register is readonly and is used as the start pointer of capabilities list. BIT 31:8 7:0 ATTRIBUTE R R BIT NAME --CAPPR Reserved. Fixed at 0. Capabilities Pointer The value is dependent on the PMEn and VPDEn loaded from EEPROM to decide the W89C841F power management and VPD capability. If PMEn = 1, CAPPR is set to DCh. If PMEn = 0 and VPDEn = 1, CAPPR is set to E4h. If PMEn = 0 and VPDEn = 0, CAPPR is set to 00h. DESCRIPTION - 41 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D F3C/FIR Interrupt Register This register stores the MAX Latency Timer and Min Grant Timer. They are loaded from EEPROM. BIT 31:24 ATTRIBUTE R BIT NAME MAXLAT Max Latency Timer Loaded from EEPROM. Indicates how often, in units of 0.25 S, W89C841F needs to gain access to PCI bus. Assuming PCI clock rate is 33 MHz. 23:16 R MINGNT Min Grant Timer Loaded from EEPROM. Indicates how long a burst period, in units of 0.25 S, is needed by W89C841F. Assuming PCI clock rate is 33 MHz. 15:8 7:0 R R/W IPIN ILINE Interrupt Pin Fixed at 01h. Indicates INTAB is used. Interrupt Line Written by power-on software to specify routing of interrupt line. DESCRIPTION F40/FSR Signature Register The register is designed for identifying the hardware of W89C841F. BIT 31:16 ATTRIBUTE R/W BIT NAME DVAR Driver Area This field is for driver special use. The driver can write some specific pattern to these bits for bundling the software and hardware of W89C841F together. 15:8 7:0 R R --SIG Reserved. Fixed at 0. Signature After the hardware reset, these 8 bits value is toggled as following SIG = 70h at (2N-1)th read 44h at 2Nth read Where N = 1, 2, .... DESCRIPTION - 42 - W89C841F/D Fdc/FPMR0 Power Management Register 0 The register provides the power management capabilities of W89C841F. BIT 31: 27 ATTRIBUTE R BIT NAME PME_SP DESCRIPTION PME_Support bit 31 = 1 --- PMEB can be asserted from D3(cold) state. The value is dependent on the auxiliary power source detection from pin BtOEB/AuxPWR after power-on reset. bit 30 = 1 --- PMEB can be asserted from D3 (hot). Fixed to 1. bit 29 = 0 --- PMEB cannot be asserted from D2. Fixed to 0. bit 28 = 1 --- PMEB can be asserted from D1. Fixed to 1. bit 27 = 1 --- PMEB can be asserted from D0. Fixed to 1. D2_Support Fixed to 0. W89C841F does not support D2 Power Management State. D1_Support Fixed to 1. W89C841F supports D1 Power Management State. 3.3V Auxiliary Current This field reports the 3.3Vaux auxiliary current requirements for PCI function. If PM_Data_En is disable and D3 cold is not supported, Aux_Current are fixed to 000b. IF PM_Data_En is disable and D3 cold is supported, Aux_Current bits apply: Bit 24 1 1 1 1 0 0 0 0 23 1 1 0 0 1 1 0 0 22 1 0 1 0 1 0 1 0 3.3VAux Max. Current Required 375 mA 320 mA 270 mA 220 mA 160 mA 100 mA 55 mA 0 (self powered) 26 R D2SUP 25 R D1SUP 24:22 R Aux_ Current If bit PM_Data_En loaded from EEPROM is enabled, PM_Data field of Fe0/FPMR1 Is implemented to report the power consumption and power dissipation of each device state (D0, D1 and D3). So it takes precedence over 3.3Vaux current requirement reporting. Aux_Current bits will be fixed to 000b. Note: The 3.3Vaux Max. auxiliary current of W89C841F is 220 mA which should be loaded from EEPROM. R --- Fixed to 0. - 43 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Fdc/FPMR0 Power Management Register 0, continued BIT 18:16 ATTRIBUTE R BIT NAME VERS DESCRIPTION Version Fixed at 010b. The W89C841F complies with Revision 1.1 of the PCI Power Management Interface Specification Next Item Pointer The value is dependent on the VPDEn loaded from EEPROM to decide the W89C841F VPD capability link list pointer. If VPDEn = 1, NXTPR is equal to E4h. If VPDEn = 0, NXTPR is equal to 00h. Capability Identifier Fixed to 01h. This linked list item is the PCI Power Management registers. 15:8 R NXTPR 7:0 R CAP_ID Fe0/FPMR1 Power Management Register 1 The register provides the power management control, status and power consumption, dissipation data of supported device power states. BIT 31:24 ATTRIBUTE R BIT NAME PM_Data DESCRIPTION PM_Data If bit PM_Data_En loaded from EEPROM is enabled, PM_Data is used to report the state dependent data requested by the D_Select field. The value is scaled by the value reported by the D_Scale field. All of the PM_data will be loaded from EEPROM after power on reset. Reserved. Fixed at 0. PME Status This bit is set when the enabled Wake-up Frame detector receives a Wake-up Frame or the enabled Magic Packet detector receives a Magic Packet or the enabled Link Status Change Detector detected a link status change independent of the state of the PME_EN bit. When PME_STS and PME_EN are set, W89C841F asserts PMEB. Writing a 1 to this bit will clear it and cause W89C841F to stop asserting a PMEB (if PME_En is enable). Writing a 0 has no effect. This bit defaults to 0 if PMEB generation from D3cold is not supported If PMEB generation from D3cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. 23:16 15 R Sticky bit, R/WC --PME_STS - 44 - W89C841F/D Fe0/FPMR1 Power Management Register 1, continued BIT 14:13 ATTRIBUTE R BIT NAME D_Scale Data Scale DESCRIPTION Indicates the scaling factor to be used when interpreting the value of the PM_Data field. The value is loaded from EEPROM. 00b = Unknown 01b = 0.1x 10b = 0.01x 11b = 0.001x 12:9 R/W D_Select Data Select Used to select which data is to be reported in units Watts through the PM_Data and D_Scale fields. 0 = D0 power Consumed 1 = D1 power Consumed 3 = D3 power Consumed 4 = D0 power Dissipated 5 = D1 power Dissipated 7 = D3 power Dissipated Others = reserved Note: The power consumption and power dissipation of W89C841F at different power state are: 1. D0: 0.59W 2. D1: 0.59W 3. D3: 0.52W 8 Sticky bit, R/W PME_EN PME Enable When set to 1, PMEB assertion is enabled. When reset to 0, PMEB assertion is disabled. When PME_STS and PME_EN are set, W89C841F asserts PMEB. This bit defaults to 0 if PMEB generation from D3cold is not supported. If PMEB generation from D3cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. 7:2 1:0 R R/W --PW_STS Reserved. Fixed at 0. Power State 00b --- Indicates W89C841F at D0 power state 01b --- Indicates W89C841F at D1 power state 11b --- Indicates W89C841F at D3 (hot) power state Writing 10b has no effect. - 45 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Fe4/FVPDR0 Vital Product Data Register 0 The register provides control and status capability for the data transfer between register Fe8/FVPDR1 and EEPROM. BIT 31 ATTRIBUTE R/W BIT NAME VPDFlag VPD Flag A flag used to indicate when the transfer of data between the VPD Data Register (FVPDR1) and EEPROM is completed. A. Read VPD information 1. Reset VPDFlag to 0, and Write VPD Address to VPDADDR. 2. VPDFlag will be set to 1, after 4 bytes data are read from EEPROM to Register FVPDR1 B. Write VPD information 1. Write the data to Register FVPDR1. 2. Set VPDFlag to 1, and write VPD Address to VPDADDR. 3. VPDFlag will be reset to 0, after 4 bytes data are written from Register FVPDR1 to EEPROM. 30:16 R/W VPDADDR VPD Address It is used to access VPD data that is stored in EEPROM. The lower 2 bits of VPDADDR must be zero. 15:8 R NEXTID Pointer to Next ID Fixed at 00h. There is no next item pointer in the capabilities list. 7:0 R VPDID VPD ID Fixed at 03h. It indicates capability structure ID for VPD DESCRIPTION Fe8/FVPDR1 Vital Product Data Register 1 The register provides the buffer for VPD from system or EEPROM. BIT 31:0 ATTRIBUTE R/W BIT NAME VPD_Data VPD Data VPD data are read or written through this register. The least significant byte of this register corresponds to the byte of VPD at the address specified by the bits VPDADDR of register Fe4/FVPDR0. DESCRIPTION - 46 - W89C841F/D 9. FUNCTION REGISTERS W89C841F implements two types of function registers: Cxx and Dxx. Cxx function registers are used to perform the function control and status monitor of W89C841F. Dxx function registers are used to control power management parameters, monitor power management status and setup wake-up frames parameters. The general attributes of W89C841F function registers are described as the following: 1) The function registers of W89C841F can be mapped into the host I/O space or memory space. 2) The registers of the W89C841F are double word aligned. Each register consists of 32 bits and may be accessed using any byte-enable combinations with double word aligned address. 3) Burst access to the registers of W89C841F will be terminated after 1st data transfer completed with a Disconnect without Data. 4) SoftReset will have the same effect as done by HardReset on the registers of W89C841F, except for the function registers C34/CMA0, C38/CMA1, D00/DWUPC - D6c/DBWF4BM3, Dcc/DPA0, Dd0/DPA1 and Df0/DFER - Dfc/DFFER and configuration registers 5) Any read on the reserved register will be returned with 0 value. Cxx Function Registers The following table outlined all the control/status registers in W89C841F, offset address, and summarized its function. CODE C00 C04 C08 C0c C10 C14 C18 C1c C20 C24 C28 C2c C30 C34 C38 C3c ABBR. CBCR CTSDR CRSDR CRDLA CTDLA CISR CIMR CNCR CFDCR CTDAR CTBAR CRDAR CRBAR CMA0 CMA1 CGTR Bus Control Transmit Start Demand Receive Start Demand Receive Descriptor List Address Transmit Descriptor List Address Interrupt Status Interrupt Mask Network Configuration Frame Discarded Counter Current Transmit Descriptor Address Current Transmit Buffer Address Current Receive Descriptor Address Current Receive Buffer Address Multicast Address 0 Multicast Address 1 General Timer Register MEANING BASE OFFSET FROM FBIOAC 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2ch 30h 34h 38h 3Ch BASE OFFSET FROM FBMA 000h 004h 008h 00Ch 010h 014h 018h 01Ch 020h 024h 028h 02ch 030h 034h 038h 03Ch - 47 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D This table lists the initial state of each register in W89C841F after Stk_ResetB, PCI_ResetB, D3toD0_ResetB and software reset. CODE C00 C04 C08 C0c C10 C14 C18 C1c C20 C24 C28 C2c C30 C34 C38 C3c ABBR. CBCR CTSDR CRSDR CRDLA CTDLA CISR CIMR CNCR CFDCR CTDAR CTBAR CRDAR CRBAR CMA0 CMA1 CGTR STK_RESETB, PCI_RESETB D3TOD0_RESETB 0001_0010h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0130h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h SOFTWARE RESET 0001_0010h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0130h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h not affected not affected 0000_0000h The detail function and operation for each register in W89C841F will be described in the following paragraph. C00/CBCR PCI Bus Control Register This register defines the configuration of PCI bus master. BIT 31:22 21 ATTRIBUTE R R/W BIT NAME ---WAIT Reserved. Fixed to 0. Wait State Insertion When WAIT is set, W89C841F as a bus master executes memory read/write with one wait state every data phase. When WAIT is reset, W89C841F as a bus master executes memory read/write with zero wait state every data phase. 20 R/W DBE Descriptor Big Endian Mode When set, the descriptors will be handled in big endian mode. When reset, the descriptors will be treated in little endian mode DESCRIPTION - 48 - W89C841F/D C00/CBCR PCI Bus Control Register, continued BIT 19:17 16 ATTRIBUTE R R/W BIT NAME --PAE Reserved. Fixed at 0. PCI Abort Enable DESCRIPTION 1: If bus error happened, TXDMA and RXDMA will halt. Driver must reinitialized W89C841F. (default) 0: If bus error happened, TXDMA and RXDMA will not halt. Wrong data will not be written into register of configuration space, Cxx or Dxx. 15:14 R/W CA Cache Alignment CA defines the address boundary for the burst access to the data transmission or reception. When the starting address of the data burst access is not aligned, more specifically, the starting address should be a multiple of some number such as 4, 8 etc. W89C841F will have the first burst transfer that causes that the next burst access will has the start address aligned. After the first burst occurred, all other burst operation are aligned with the configuration of CA accordingly. The CA must be initialized with a non-zero value after reset. The alignment configuration is as following: [00] [01] [10] [11] 13:8 R/W BL Burst Length BL defines the maximum number of the double words that can be transferred within one PCI burst transaction. The burst length configuration is as following. 00h 01h 02h 04h 08h 10h 20h other Refer to CA 1 double word 2 double word 4 double word 8 double word 16 double word 32 double word Reserved Reserved (default) 8 double word alignment 16 double word alignment 32 double word alignment - 49 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D C00/CBCR PCI Bus Control Register, continued BIT 7 ATTRIBUTE R/W BIT NAME BBE DESCRIPTION Buffer With Big Endian When set, the data buffers are treated with big endian ordering. When reset, the data buffers are treated with little endian ordering. 6:2 R/W SKIP Skip Length Between Descriptors This field specifies the skip length between two descriptors from the start address of the current descriptor to the start address of the next descriptor. The unit of the skip length is double word. The default value after hardware reset is 04h. 1 R/W ARB Arbitration Between Tx and Rx Processes When reset, the TX process and RX process will have the right to use the internal bus with the same priority. When set, the RX process will have higher priority than TX process with regarding to the internal bus utilization. 0 R/W SWR Software Reset. Set bit SW_Reset to high will reset most internal registers except registers C34/CMA0, C38/CMA1, D00/DWUPC - D6c /DBWF4BM3, Dcc/CPA0, Dd0/CPA1, Df0/DFER - Dfc /DFFER and PCI Configuration Registers. C04/CTSDR Transmit Start Demand Register This register is used to request W89C841F to do a transmission process. BIT 31:0 ATTRIBUTE W BIT NAME TSD DESCRIPTION Transmit Start Demand A write to this register will trigger W89C841F transmit DMA to fetch the descriptor for progressing the transmission operation when W89C841F transmit DMA is staying at the suspend state. Otherwise, the write operation will have no effect. - 50 - W89C841F/D C08/CRSDR Receive Start Demand Register The register is used to request W89C841F to do a receive process. BIT 31:0 ATTRIBUTE W BIT NAME RSD Receive Start Demand A write to this register will trigger W89C841F receive DMA to fetch the descriptor for progressing the receiving operation when W89C841F receive DMA is staying at the suspend state. Otherwise, the write operation will have no effect. DESCRIPTION C0c/CRDLA Receive Descriptors List Addresses The register defines the start address of the receive descriptor list. It should be updated only when the receive DMA state machine is staying at the stop state. BIT 31:2 1:0 ATTRIBUTE R/W R/W BIT NAME SRL MBZ DESCRIPTION Start address of Receive List Must be written as 0 for double word alignment. C10/CTDLA Transmit Descriptors List Addresses The register defines the start address of the transmit descriptor list. It should be updated only when the transmission DMA state machine is staying at the stop state. BIT 31:2 1:0 ATTRIBUTE R/W R/W BIT NAME STL MBZ DESCRIPTION Start address of Transmit List Must be written as 0 for double word alignment. C14/CISR Interrupt Status Register Most bits of this register report the interrupt status. The assertion of the interrupt status, reported by bits 0 to bit 14 and the corresponding interrupt mask bits will cause a hardware interrupt to the host. A write with 1 value the status bit will clear them and write 0 will have no effect. - 51 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D C14/CISR Interrupt Status Register, continued BIT 31:26 25:23 ATTRIBUTE R R BIT NAME --BET Bus Error Type DESCRIPTION Reserved. Fixed at 0. The field indicates the error type of bus error and is valid only when bit 13, bus error, is set. Assertion of these bits does not generate interrupt. The definition of bus error is as follows. 000 = Parity Error (Master Mode) 001 = Master Abort (Master Mode) 010 = Target Abort (Master Mode) 011 = Signaled System Error (Slave Mode) 100 = Data Parity Error (Slave Mode) 101 - 111 = Reserved The initial state of this field after reset is 0. 22:20 R TPS Transmit Process State This field indicates the transmit state. This field does not generate interrupt. 19:17 R RPS Receive Process State This field indicates the receive state. This field does not generate interrupt. 16 R NIR Normal Interrupt Report The normal interrupt report includes transmit completed interrupt, transmit buffer unavailable interrupt, the receive completed interrupt and the receive pause packet interrupt. The NIR is a logical OR result of the bits 0, 2, 6, 14 of register C14/CISR. Only the bits corresponding to the unmasked bits of C18/CIMR will affect this bit. 15 R AIR Abnormal Interrupt Report The abnormal interrupt includes transmit process in idle state interrupt, receive early interrupt, receive error interrupt, transmit FIFO under-flow interrupt, receive buffer unavailable interrupt, receive in idle state interrupt, EEPROM Programming Fail Interrupt, transmit early interrupt, timer expire interrupt, PHY Interrupt and the bus error interrupt. The AIR is a logical OR result of the bits 1, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 of register C14/CISR. Only these bits corresponding to the unmasked bits of the C18/CIMR will affect this bit. - 52 - W89C841F/D C14/CISR Interrupt Status Register, continued BIT 14 13 ATTRIBUTE R/WC R/WC BIT NAME RPP BE DESCRIPTION Receive Pause Packet Interrupt A high indicates a pause packet is received. Bus Error Interrupt A high indicates a bus error happened. The error type will be shown by bit 25 - 23. 12 R PI PHY Interrupt A high indicates a PHY interrupt happened. PHY interrupt event is stored in Global Interrupt Status Register [address 14h] of MII Management. After reading Global Interrupt Status Register, that register and this bit will be cleared. 11 R/WC TE Timer Expired Interrupt A high indicates the general timer of register C3c/CGTR expired. 10 R/WC TEI Transmit Early Interrupt W89C841F will has Transmit Early Interrupt status set after the packet to be transmitted is completely transferred into the transmit FIFO if Transmit Early Interrupt On bit of C1c/CNCR[30] is set. The TEI will be cleared automatically after the packet is transmitted out from the transmit FIFO completely. 9 R/WC EPF EEPROM Programming Fail Interrupt A high indicates a programming error happened when W89C841F tries to write data into EEPROM that is in write protected state. 8 R/WC RIDLE Receive in Idle State Set means the receive DMA state machine is in the idle state. 7 R/WC RBU Receive Buffer Unavailable When there is no receive buffer available, this bit is set and the receive process enters the suspend state. 6 R/WC RINT Receive Complete Interrupt A high indicates that a frame has been received and the receive status is transferred into the receive descriptors of the current frame. 5 R/WC TUF Transmit FIFO Under-flow A high indicates that the transmit FIFO had an under-flow error during the packet transmission. - 53 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D C14/CISR Interrupt Status Register, continued BIT 4 ATTRIBUTE R/WC BIT NAME RERR Receive Error DESCRIPTION A high indicates that the receive DMA detects a receive error during the packet reception. 3 R/WC REI Receive Early Interrupt The REI will be set when the number of the data of the incoming frame, in double word unit, transferred to the data buffer reaches Receive Early Interrupt Threshold specified by the register C1c/CNCR[28:21] if Receive Early Interrupt On in the register C1c/CNCR[31] is set. 2 R/WC TBU Transmit Buffer Unavailable A high indicates that there is no available transmit descriptor during or after the packet transmission. 1 R/WC TIDLE Transmit Process in Idle State A high indicates the transmit state machine is in the idle state. 0 R/WC TINT Transmit Complete Interrupt The TINI will be set when a frame transmission is completed and the FINT (bit 31) of Transmit Descriptor 1 (T01) is set. C18/CIMR Interrupt Mask Register The register controls the interrupt enable corresponding to the bits in the register C14/CISR BIT 31:17 16 ATTRIBUTE R R/W BIT NAME ---NIE Reserved. Fixed to 0. Normal Interrupt Enable The Normal Interrupt will be enabled if the NIE is set to high. The Normal Interrupt is disabled when the NIE is reset to low. The hardware interrupt will be asserted if both the NIE bit of the C18/CIMR[16] and the NIR bit of the C14/CISR[16] are set to high. 15 R/W AIE Abnormal Interrupt Enable The Abnormal Interrupt will be enabled if the AIE is set to high. The Abnormal Interrupt is disabled when the AIE is reset to low. The hardware interrupt will be asserted if both the AIE bit of the C18/CIMR[15] and the AIR bit of the C14/CISR[15] are set to high. DESCRIPTION - 54 - W89C841F/D C18/CIMR Interrupt Mask Register, continued BIT 14 ATTRIBUTE R/W BIT NAME RPPE DESCRIPTION Receive Pause Packet Interrupt Enable The receive pause packet Interrupt will be enabled if both AIE and BPPE are set to high, otherwise, the receive pause packet Interrupt will be disabled. 13 R/W BEE Bus Error Enable The Bus Error Interrupt will be enabled if both AIE and BEE are set to high, otherwise, the Bus Error Interrupt will be disabled. 12 R/W PIE PHY Interrupt Enable. The PHY Interrupt will be enabled if both AIE and PIE are set to high, otherwise, the PHY Interrupt will be disabled. 11 R/W TEE Timer Expired Enable The Timer Expired Interrupt will be enabled if both AIE and TEE are set to high, otherwise, the Timer Expired Interrupt will be disabled. 10 R/W TEIE Transmit Early Interrupt Enable The Transmit Early Interrupt will be enabled if both AIE and TEIE are set to high, otherwise, the Transmit Early Interrupt will be disabled. 9 R/W EPFE EEPROM Programming Fail Enable: The EEPROM Programming Fail will be enabled if both AIE and EPFE are set to high, otherwise, the EEPROM Programming Fail will be disabled. 8 R/W RIE Receive Idle Enable. The Receive Idle Interrupt will be enabled if both AIE and RIE are set to high, otherwise, the Receive Idle Interrupt will be disabled. 7 R/W RBUE Receive Buffer Unavailable Enable. The Receive Buffer Unavailable Interrupt will be enabled if both AIE and RBUE are set to high, otherwise, the Receive Buffer Unavailable Interrupt will be disabled. 6 R/W RINTE Receive Complete Interrupt Enable The Receive Interrupt will be enabled if both NIE and RINTE are set to high, otherwise, the Receive Interrupt will be disabled. 5 R/W TFUE Transmit FIFO Underflow Enable The Transmit FIFO Underflow Interrupt will be enabled if both AIE and TFUE are set to high, otherwise, the Transmit FIFO Underflow Interrupt will be disabled. - 55 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D C18/CIMR Interrupt Mask Register, continued BIT 4 ATTRIBUTE R/W BIT NAME RERRE Receive Error Enable DESCRIPTION The Receive Error Interrupt will be enabled if both AIE and RERRE are set to high, otherwise, the Receive Error Interrupt will be disabled. 3 R/W REIE Receive Early Interrupt Enable The Receive Early Interrupt will be enabled if both AIE and REIE are set to high, otherwise, the Receive Early Interrupt will be disabled. 2 R/W TBUE Transmit Buffer Unavailable Enable The Transmit Buffer Unavailable Interrupt will be enabled if both NIE and TBUE are set to high, otherwise, the Transmit Buffer Unavailable Interrupt will be disabled. 1 R/W TIE Transmit Idle Enable The Transmit Idle Interrupt will be enabled if both AIE and TIE are set to high, otherwise, the Transmit Idle Interrupt will be disabled. 0 R/W TINTE Transmit Complete Interrupt Enable The Transmit Interrupt will be enabled if both NIE and TINTE are set to high, otherwise, the Transmit Interrupt will be disabled. C1c/CNCR Network Configuration Register The register defines the configuration for the data transmission or reception and the interrupt algorithm for interrupt assertion. BIT 31 ATTRIBUTE R/W BIT NAME REIO DESCRIPTION Receive Early Interrupt On The receive early interrupt function will be enabled when the REIO is set to high. Otherwise, receive early interrupt function will be disabled. 30 R/W TEIO Transmit Early Interrupt On The transmit early interrupt function will be enabled when the TEIO is set to high. Otherwise, transmit early interrupt function will be disabled. 29 R ES Ethernet Speed 1: 100 Mbps 0: 10 Mbps. - 56 - W89C841F/D C1c/CNCR Network Configuration Register, continued BIT 28:21 ATTRIBUTE R/W BIT NAME REIT DESCRIPTION Receive Early Interrupt Threshold During receiving packet, the W89C841F will assert an interrupt request when the bytes number of the received data, which the receive DMA has moved them into the data buffer, excesses receive early interrupt threshold. To set this field 00H will disable receive early interrupt function. The setting of receive early interrupt threshold is as following. 01h 4 bytes 02h 8 bytes -0fh --60 bytes -- 10h 64 bytes FFh 1020 bytes 20:14 R/W TTH Transmit Threshold These bits select the transmit threshold level of the transmit FIFO. The packet Transmission will be started immediately once the data queued into the transmit FIFO has reached the threshold level. The transmission will also be started immediately when the full packet has been transferred into the transmit FIFO even though the frame length is less than the TTH level. To change this bit, the transmit state machine must be in Idle state. The following table shows there is a difference with 16 bytes for each consecutive setting value in this field, except that the first one in the table. 00h full packet 01h 16 bytes 02h 32 bytes -- -0Fh 240 bytes 10h 256 bytes -- -7Fh 2032 bytes 13 R/W TXON Transmit On When set, the transmission process will be started. When reset, the transmission state machine will be stopped after the current frame is completed - 57 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D C1c/CNCR Network Configuration Register, continued BIT 12 ATTRIBUTE R/W BIT NAME VLANEN VLAN Enable DESCRIPTION 1: W89C841F can transmit and receive packet with VLAN tagged whose maximum length is equal to 1522 bytes. 0: Only untagged frame are transmitted and received. Packet length up to 1518 bytes is allowed. (default) 11:10 R/W LBK Loopback Mode The LBK selects the W89C841F loop-back modes: 00 01 10 Reserved Normal mode (default) Internal Loop-back External Loop-back 9 R FD Full Duplex Mode 1: Full duplex mode. 0: Half duplex mode. 8 R/W ADP Accept Directed Packet When set, all incoming packets with a directed address will be accepted. 7 R/W AEP Accept Error Packet When set, all incoming CRC error packets passed address filtering will be accepted. 6 R/W ARP Accept Runt Packet When set, the incoming packets pass the address filtering with the length less than 64 bytes are accepted. 5 R/W ABP Accept Broadcast Packet. When set, all incoming packets with a Broadcast address will be accepted. 4 R/W AMP Accept Multicast Packet When set, all incoming packets with a multicast address match the node multicast address table (MAR7 - MAR0) will be accepted. 3 R/W APP Accept All Physical Packet When set, all incoming packets with unicast address will be accepted. - 58 - W89C841F/D C1c/CNCR Network Configuration Register, continued BIT 2 ATTRIBUTE R/W BIT NAME RXON Receive On. DESCRIPTION When set, the receive process will be started. When reset, the receive state machine will be stopped after the current frame is completed. 1 R/W TFCEN TX Flow Control Enable 1: W89C841F can transmit Pause packet. 0: W89C841F can not transmit Pause packet. (default) 0 R/W RFCEN RX Flow Control Enable 1: W89C841F can parse Pause packet. 0: W89C841F can not parse Pause packet. (default) C20/CFDCR Frame Discarded Counter Register The register records the missed packet count and the FIFO overflow count. BIT 31 ATTRIBUTE RC BIT NAME MRFO DESCRIPTION More Receive FIFO Overflow This bit is the overflow bit of the receive FIFO Overflow counter. The actual number of the FIFO overflow must be more than the number shown by the bits RFOC if the MRFO is set to high. This bit will be clear after read. 30:16 RC RFOC Receive FIFO Overflow Counter The RFOC indicates the number of the packets that are discarded due to the receive FIFO overflow under the condition of the receive buffer is not available. This counter will be clear after read. 15 RC MMP More Missed Packets Overflow bit of Missed Packet Counter. The actual number of the missed packet must be more than the number shown by the bits field MPC if MMP is set tot high. This bit will be clear after read. 14:0 RC MPC Missed Packet Counter The MPC indicates the number of packets that are discarded due to the receive FIFO overflow. This counter will be clear after read. - 59 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D C24/CTDAR Current Transmit Descriptor Address Register The register shows the start address of the descriptor which W89C841F transmit DMA state machine is used to process the current frame. BIT 31:0 ATTRIBUTE R BIT NAME CTDA DESCRIPTION Current Transmit Descriptor Address The CTDA represents the start address of the current receive descriptor which W89C841F transmit DMA state machine is used to process the transmit frame. C28/CTBAR Current Transmit Buffer Address Register The register shows the address of the system memory from which W89C841F transmit DMA state machine will fetch the double word data and queue the data into the FIFO for transmission. BIT 31:0 ATTRIBUTE R BIT NAME CTBA DESCRIPTION Current Receive Buffer Address The CTBA contains the start address of the host memory from which W89C841F transmit DMA state machine will fetch the double word data and queue it into the FIFO for transmission. C2c/CRDAR Current Receive Descriptor Address Register The register shows the start address of the receive descriptor which is used by W89C841F receive DMA state machine to process the current receive frame. BIT 31:0 ATTRIBUTE R BIT NAME CRDA DESCRIPTION Current Receive Descriptor Address The CRDA represents the start address of the current receive descriptor which W89C841F receive DMA state machine is used to process the received frame. C30/CRBAR Current Receive Buffer Address Register The register shows the start address of the host memory which is used by W89C841F receive DMA state machine to store the current aligned double word data of the current received frame. BIT 31:0 ATTRIBUTE R BIT NAME CRBA DESCRIPTION Current Receive Buffer Address The CRBA contains the pointer current address in the onusing buffer of the host memory which will be used by W89C841F receive DMA state machine to store the current aligned double word data of the current received frame. - 60 - W89C841F/D C34/CMA0 Multicast Address Register 0 The register defines the lower 32 bits of the total 64 bits multicast address hashing table. BIT 31:24 23:16 15:8 7:0 ATTRIBUTE R/W R/W R/W R/W BIT NAME MAR3 MAR2 MAR1 MAR0 Muticast Address 3 The MAR3 defines the bit 31 - 24 of the hashing table. Muticast Address 2 The MAR2 defines the bit 23 - 16 of the hashing table. Muticast Address 1 The MAR1 defines the bit 15 - 8 of the hashing table. Muticast Address 0 The MAR0 defines the bit 7 - 0 of the hashing table. DESCRIPTION C38/CMA1 Multicast Address Register 1 The register defines the upper 32 bits of the 64 bits multicast address hashing table. BIT 31:24 23:16 15:8 7:0 ATTRIBUTE R/W R/W R/W R/W BIT NAME MAR7 MAR6 MAR5 MAR4 Muticast Address 7 The MAR7 defines the bit 63 - 56 of the hashing table. Muticast Address 6 The MAR2 defines the bit 55 - 48 of the hashing table. Muticast Address 5 The MAR1 defines the bit 47 - 40 of the hashing table. Muticast Address 4 The MAR4 defines the bit 39 - 32 of the hashing table. DESCRIPTION C3c/CGTR General Timer Register The register shows the real time content of W89C841F internal general timer. BIT 31 ATTRIBUTE R/W BIT NAME ATLP DESCRIPTION Accept Too Long Packet When set, a packet whose length is longer than 1518 (1522) bytes is received. When reset, a packet whose length is longer than 1518 (1522) bytes is not received. Default to 0. 30:17 R --Reserved. Fixed at 0. - 61 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D C3c/CGTR General Timer Register, continued BIT 16 ATTRIBUTE R/W BIT NAME RECUR Recursive Mode DESCRIPTION 1: The value of bits Timer in the register C3c/CGTR[15:0] can be reloaded for internal general timer to count down when the internal general reaches zero. 0: No recursive to the internal general timer. (default) 15:0 R/W TIMER General Timer The bits TIMER shows the content of the general timer inside the W89C841F. The internal general timer will count down from the pre-set value, a non zero value, programmed by the driver automatically. The time unit for the internal general timer count_down is approximately 2048 times the cycle duration of the MII TXCLK. For instance, the count down time unit for a 25 MHz MII TXCLK is approximately 82 S. Dxx Function Registers The following table outlined all the Dxx function registers for power management control and status, EEPROM, Boot ROM, PHY's Registers access and CardBus status/event in W89C841F. CODE ABBR. MEANING BASE OFFSET FROM FBIOAD 00h 0Ch 10h 14h 20h 24h 28h 2Ch 30h 34h 38h 3Ch BASE OFFSET FROM FBMA 100h 10Ch 110h 114h 120h 124h 128h 12Ch 130h 134h 138h 13Ch D00 D04 - D08 D0c D10 D14 D18 - D1C D20 D24 D28 D2c D30 D34 D38 D3C DWUPC Reserved DWF0CRC DWF1CRC DWF2CRC Reserved DBWF0BM0 DBWF0BM1 DBWF0BM2 DBWF0BM3 DBWF1BM0 DBWF1BM1 DBWF1BM2 DBWF1BM3 Wake-up Control and Status Wake-up Frame B0B1 CRC Wake-up Frame B2B3 CRC Wake-up Frame B4 CRC Basic Wake-up Frame 0 Byte-Mask 0 Basic Wake-up Frame 0 Byte-Mask 1 Basic Wake-up Frame 0 Byte-Mask 2 Basic Wake-up Frame 0 Byte-Mask 3 Basic Wake-up Frame 1 Byte-Mask 0 Basic Wake-up Frame 1 Byte-Mask 1 Basic Wake-up Frame 1 Byte-Mask 2 Basic Wake-up Frame 1 Byte-Mask 3 - 62 - W89C841F/D Dxx Function Registers, continued CODE ABBR. MEANING BASE OFFSET FROM FBIOAD 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch BASE OFFSET FROM FBMA 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h 16Ch D40 D44 D48 D4c D50 D54 D58 D5c D60 D64 D68 D6c D70 - Dbc Dc0 Dc4 Dc8 Dcc Dd0 Dd4 Dd8 Ddc Df0 Df4 Df8 Dfc DBWF2BM0 DBWF2BM1 DBWF2BM2 DBWF2BM3 DBWF3BM0 DBWF3BM1 DBWF3BM2 DBWF3BM3 DBWF4BM0 DBWF4BM1 DBWF4BM2 DBWF4BM3 --DBRAR DEEAR DMMAR DPA0 DPA1 ----DRFCTV DFER DFEMR DFPSR DFFER Basic Wake-up Frame 2 Byte-Mask 0 Basic Wake-up Frame 2 Byte-Mask 1 Basic Wake-up Frame 2 Byte-Mask 2 Basic Wake-up Frame 2 Byte-Mask 3 Basic Wake-up Frame 3 Byte-Mask 0 Basic Wake-up Frame 3 Byte-Mask 1 Basic Wake-up Frame 3 Byte-Mask 2 Basic Wake-up Frame 3 Byte-Mask 3 Basic Wake-up Frame 4 Byte-Mask 0 Basic Wake-up Frame 4 Byte-Mask 1 Basic Wake-up Frame 4 Byte-Mask 2 Basic Wake-up Frame 4 Byte-Mask 3 Reserved Boot ROM Access EEPROM Access MII Management Access Physical Address 0 Physical Address 1 Reserved Reserved RXDMA Flow Control Threshold Value Function Event Register Function Event Mask Register Function Present Status Register Function Force Event Register C0h C4h C8h CCh D0h 1C0h 1C4h 1C8h 1CCh 1D0h DCh F0h F4h F8h FCh 1DCh 1F0h 1F4h 1F8h 1FCh - 63 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D This table lists the initial state of each register in W89C841F after Stk_ResetB, PCI_ResetB, D3toD0_ResetB and software reset. CODE D00 D04 - D08 D0C D10 D14 D18 - D1c D20 D24 D28 D2C D30 D34 D38 D3C D40 D44 D48 D4c D50 D54 D58 D5c D60 D64 D68 D6c D70 - Dbc Dc0 Dc4 Dc8 Dcc ABBR. DWUPC Reserved DWF0CRC DWF1CRC DWF2CRC Reserved DBWF0BM0 DBWF0BM1 DBWF0BM2 DBWF0BM3 DBWF1BM0 DBWF1BM1 DBWF1BM2 DBWF1BM3 DBWF2BM0 DBWF2BM1 DBWF2BM2 DBWF2BM3 DBWF3BM0 DBWF3BM1 DBWF3BM2 DBWF3BM3 DBWF4BM0 DBWF4BM1 DBWF4BM2 DBWF4BM3 Reserved DBRAR DEEAR DMMAR DPA0 0000_0000h 0000_0000h 4020_0000h 0000_0000h 0000_0000h 0000_0000h 4020_0000h Non affected 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0000_0000h Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected Non affected FFFE_FFFEh FFFE_FFFEh FFFE_0000h Non affected Non affected Non affected STK_RESETB, PCI_RESETB, D3TOD0_RESETB 0000_0458h SOFTWARE RESET Non affected - 64 - W89C841F/D Continued CODE Dd0 Dd4 Dd8 Ddc Df0 Df4 Df8 Dfc ABBR. DPA1 Reserved Reserved DRFCTV DFER DFEMR DFPSR DFFER STK_RESETB, PCI_RESETB, D3TOD0_RESETB 0000_0000h SOFTWARE RESET Non affected 0003_0100h 0000_0000h 0000_0000h 0000_0000h 0000_0000h 0003_0100h Non affected Non affected Non affected Non affected D00/DWUPCS Wake-up Control and Status Register BIT 31 ATTRIBUTE R/WC BIT NAME RMGP DESCRIPTION Received Magic Packet When set, indicates that a Magic Packet has been received if Magic Packet detector is enabled. 30 R/WC DLSCD_ L2F Detected Link Status Change From Link to Fail When set, indicates that a Link Status Change From Link to Fail if Link Status Changes From Link to Fail Detector Enable (LSCDE_L2F = 1). Detected Link Status Change From Fail to Link When set, indicates that a Link Status Change From Fail to Link if Link Status Changes From Fail to Link Detector Enable (LSCDE_F2L = 1). Reserved. Fixed to 0. Received Wake-up Frame 4 When set, indicates that a Wake-up Frame 4 has been received if Wake-up Frame detector is enabled (WUPFE= 1). 19 R/WC RWUPF3 Received Wake-up Frame 3 When set, indicates that a Wake-up Frame 3 has been received if Wake-up Frame detector is enabled (WUPFE= 1). 18 R/WC RWUPF2 Received Wake-up Frame 2 When set, indicates that a Wake-up Frame 2 has been received if Wake-up Frame detector is enabled (WUPFE= 1). 29 R/WC DLSCD_ F2L 28:21 20 R R/WC --RWUPF4 - 65 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D D00/DWUPCS Wake-up Control and Status Register, continued BIT 17 ATTRIBUTE R/WC BIT NAME RWUPF1 DESCRIPTION Received Wake-up Frame 1 When set, indicates that a Wake-up Frame 0 has been received if Wake-up Frame detector is enabled (WUPFE = 1). 16 R/WC RWUPF0 Received Wake-up Frame 0 When set, indicates that a Wake-up Frame 0 has been received if Wake-up Frame detector is enabled (WUPFE = 1). 15:14 13 R R/W --PWRDN Reserved. Fixed at 0. PHY Power Down Enable If Bus Type is CardBus which is loaded from EEPROM, bit PWRDN is default to high (active) to force PHY into power down mode after power on reset. If Bus Type is not CardBus, bit PWRDN is default to low to disable power down mode after power on reset. 1: PHY power down enable 0: PHY power down disable 12 R EETYPE EEPROM Type After power on reset, EEPROM type will be latched in from pin BtWEB/EESel. 1: 93C56 0: 93C46 11 R/W CLKRUN_En CLOCKRUN Enable This bit is loaded from EEPROM to control pin CLKRUNB in MiniPCI or CardBus system. 1: Enable ClockRun function. 0: Disable ClockRun function. 10 R/W MGPE Magic Packet Detector Enable Loaded from EEPROM. Setting to 1 and PMEN bit is true enable the operation of Magic Packet Detector. 9 R/W LSCDE_L2F Link Status Change From Link to Fail Detector Enable Setting to 1 and PMEN bit is true enable the operation of Link Status Change From Link to Fail Detector. - 66 - W89C841F/D D00/DWUPCS Wake-up Control and Status Register, continued BIT 8 ATTRIBUTE R/W BIT NAME LSCDE_F2L DESCRIPTION Link Status Change From Fail to Link Detector Enable Setting to 1 and PMEN bit is true enable the operation of Link Status Change From Fail to Link Detector. 7 R/W WUPFE Wake-up Frame Detector Enable Setting to 1 and PMEN bit is true enable the operation of Wake-up Frame Detector. 6 R/W PMEN Power Management Enable Loaded from EEPROM. 1: PM enable, => Function PMEB and WOL function are enabled. 0: PM disable (default) => Function PMEB and WOL are all disable. Bits MGPE, LSCDE_L2F, LSCDE_F2L and WUPFE are all fixed to 0. 5 R/W VPDEN Vital Product Data Enable Loaded from EEPROM. 1: VPD data is stored in EEPROM. 0: VPD data is not stored in EEPROM. (default) 4:3 R/W WOLTP Wake ON LAN Signal Type It indicates the signal type of pin WOL/CSTSCHG. 00: Negative Pulse (125ms) 01: Positive Pulse (125ms) 10: Active Low 11: Active High (Default) 2 R AUXPWR Aux Power Status This bit is loaded from pin BtOEB/AuxPWR to indicate auxiliary power status. 1: Aux Power is ON. 0: Aux Power is OFF. 1:0 R BUSTP PC Bus Type These 2 bits are loaded from EEPROM to configure W89C841F PC Bus type. 00: PCI 01: MiniPCI 10: CardBus 11: reserved. - 67 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D D0c/DWBF0CRC Wake-up Frame B0B1 CRC Register BIT 31:16 15:0 ATTRIBUTE R/W R/W BIT NAME WFB0CRC WFB1CRC DESCRIPTION CRC-16 value for Basic Wake-up Frame 0 match Setting to all 1's except bit[16], after power-on reset. CRC-16 value for Basic Wake-up Frame 1 match Setting to all 1's except bit[0], after power-on reset. D10/DWF1CRC Wake-up Frame B2B3 CRC Register BIT 31:16 15:0 ATTRIBUTE R/W R/W BIT NAME WFB2CRC WFB3CRC DESCRIPTION CRC-16 value for Basic Wake-up Frame 2 match Setting to all 1's except bit[16], after power-on reset. CRC-16 value for Basic Wake-up Frame 3 match Setting to all 1's except bit[0], after power-on reset. D14/DWF2CRC Wake-up Frame B4 CRC Register BIT 31:16 15:0 ATTRIBUTE R/W R BIT NAME WFB4CRC WFB3CRC DESCRIPTION CRC-16 value for Basic Wake-up Frame 4 match Setting to all 1's except bit[16], after power-on reset. Reserved. Fixed to 0. D20/DBWF0BM0 Basic Wake-up Frame 0 Byte-Mask 0 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF0BM0 DESCRIPTION Basic Wake-up Frame 0 Byte-Mask 0 The bit 0 is the byte 1 mask of Basic Wake-up Frame 0. --The bit 31 is the byte 32 mask of Basic Wake-up Frame 0. Setting to 0, after power-on reset. D24/DBWF0BM1 Basic Wake-up Frame 0 Byte-Mask 1 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF0BM1 DESCRIPTION Basic Wake-up Frame 0 Byte-Mask 1 The bit 0 is the byte 33 mask of Basic Wake-up Frame 0. --The bit 31 is the byte 64 mask of Basic Wake-up Frame 0. Setting to 0, after power-on reset. - 68 - W89C841F/D D28/DBWF0BM2 Basic Wake-up Frame 0 Byte-Mask 2 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF0BM2 DESCRIPTION Basic Wake-up Frame 0 Byte-Mask 2 The bit 0 is the byte 65 mask of Basic Wake-up Frame 0. --The bit 31 is the byte 96 mask of Basic Wake-up Frame 0. Setting to 0, after power-on reset. D2c/DBWF0BM3 Basic Wake-up Frame 0 Byte-Mask 3 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF0BM3 DESCRIPTION Basic Wake-up Frame 0 Byte-Mask 3 The bit 0 is the byte 97 mask of Basic Wake-up Frame 0. --The bit 31 is the byte 128 mask of Basic Wake-up Frame 0. Setting to 0, after power-on reset. D30/DBWF1BM0 Basic Wake-up Frame 1 Byte-Mask 0 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF1BM0 DESCRIPTION Basic Wake-up Frame 1 Byte-Mask 0 The bit 0 is the byte 1 mask of Basic Wake-up Frame 1. --The bit 31 is the byte 32 mask of asic Wake-up Frame 1. Setting to 0, after power-on reset. D34/DBWF1BM1 Basic Wake-up Frame 1 Byte-Mask 1 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF1BM1 DESCRIPTION Basic Wake-up Frame 1 Byte-Mask 1 The bit 0 is the byte 33 mask of Basic Wake-up Frame 1. --The bit 31 is the byte 64 mask of Basic Wake-up Frame 1. Setting to 0, after power-on reset. D38/DBWF1BM2 Basic Wake-up Frame 1 Byte-Mask 2 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF1BM2 DESCRIPTION Basic Wake-up Frame 1 Byte-Mask 2 The bit 0 is the byte 65 mask of Basic Wake-up Frame 1. --The bit 31 is the byte 96 mask of Basic Wake-up Frame 1. Setting to 0, after power-on reset. - 69 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D D3c/DBWF1BM3 Basic Wake-up Frame 1 Byte-Mask 3 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF1BM3 DESCRIPTION Basic Wake-up Frame 1 Byte-Mask 3 The bit 0 is the byte 97 mask of Basic Wake-up Frame 1. --The bit 31 is the byte 128 mask of Basic Wake-up Frame 1. Setting to 0, after power-on reset. D40/DBWF2BM0 Basic Wake-up Frame 2 Byte-Mask 0 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF2BM0 DESCRIPTION Basic Wake-up Frame 2 Byte-Mask 0 The bit 0 is the byte 1 mask of Basic Wake-up Frame 2. --The bit 31 is the byte 32 mask of Basic Wake-up Frame 2. Setting to 0, after power-on reset. D44/DBWF2BM1 Basic Wake-up Frame 2 Byte-Mask 1 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF2BM1 DESCRIPTION Basic Wake-up Frame 2 Byte-Mask 1 The bit 0 is the byte 33 mask of Basic Wake-up Frame 2. --The bit 31 is the byte 64 mask of Basic Wake-up Frame 2. Setting to 0, after power-on reset. D48/DBWF2BM2 Basic Wake-up Frame 2 Byte-Mask 2 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF2BM2 DESCRIPTION Basic Wake-up Frame 2 Byte-Mask 2 The bit 0 is the byte 65 mask of Basic Wake-up Frame 2. --The bit 31 is the byte 96 mask of Basic Wake-up Frame 2. Setting to 0, after power-on reset. D4c/DBWF2BM3 Basic Wake-up Frame 2 Byte-Mask 3 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF2BM3 DESCRIPTION Basic Wake-up Frame 2 Byte-Mask 3 The bit 0 is the byte 97 mask of Basic Wake-up Frame 2. --The bit 31 is the byte 128 mask of Basic Wake-up Frame 2. Setting to 0, after power-on reset. - 70 - W89C841F/D D50/DBWF3BM0 Basic Wake-up Frame 3 Byte-Mask 0 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF3BM0 DESCRIPTION Basic Wake-up Frame 3 Byte-Mask 0 The bit 0 is the byte 1 mask of Basic Wake-up Frame 3. --The bit 31 is the byte 32 mask of Basic Wake-up Frame 3. Setting to 0, after power-on reset. D54/DBWF3BM1 Basic Wake-up Frame 3 Byte-Mask 1 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF3BM1 DESCRIPTION Basic Wake-up Frame 3 Byte-Mask 1 The bit 0 is the byte 33 mask of Basic Wake-up Frame 3. --The bit 31 is the byte 64 mask of Basic Wake-up Frame 3. Setting to 0, after power-on reset. D58/DBWF3BM2 Basic Wake-up Frame 3 Byte-Mask 2 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF3BM2 DESCRIPTION Basic Wake-up Frame 3 Byte-Mask 2 The bit 0 is the byte 65 mask of Basic Wake-up Frame 3. --The bit 31 is the byte 96 mask of Basic Wake-up Frame 3. Setting to 0, after power-on reset. D5c/DBWF3BM3 Basic Wake-up Frame 3 Byte-Mask 3 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF3BM3 DESCRIPTION Basic Wake-up Frame 3 Byte-Mask 3 The bit 0 is the byte 97 mask of Basic Wake-up Frame 3. --The bit 31 is the byte 128 mask of Basic Wake-up Frame 3. Setting to 0, after power-on reset. - 71 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D D60/DBWF4BM0 Basic Wake-up Frame 4 Byte-Mask 0 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF4BM0 DESCRIPTION Basic Wake-up Frame 4 Byte-Mask 0 The bit 0 is the byte 1 mask of Basic Wake-up Frame 4. --The bit 31 is the byte 32 mask of Basic Wake-up Frame 4. Setting to 0, after power-on reset. D64/DBWF4BM1 Basic Wake-up Frame 4 Byte-Mask 1 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF4BM1 DESCRIPTION Basic Wake-up Frame 4 Byte-Mask 1 The bit 0 is the byte 33 mask of Basic Wake-up Frame 4. --The bit 31 is the byte 64 mask of Basic Wake-up Frame 4. Setting to 0, after power-on reset. D68/DBWF4BM2 Basic Wake-up Frame 4 Byte-Mask 2 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF4BM2 DESCRIPTION Basic Wake-up Frame 4 Byte-Mask 2 The bit 0 is the byte 65 mask of Basic Wake-up Frame 4. --The bit 31 is the byte 96 mask of Basic Wake-up Frame 4. Setting to 0, after power-on reset. D6c/DBWF4BM3 Basic Wake-up Frame 4 Byte-Mask 3 Register BIT 31:0 ATTRIBUTE R/W BIT NAME WF4BM3 DESCRIPTION Basic Wake-up Frame 4 Byte-Mask 3 The bit 0 is the byte 97 mask of Basic Wake-up Frame 4. --The bit 31 is the byte 128 mask of Basic Wake-up Frame 4. Setting to 0, after power-on reset. - 72 - W89C841F/D Dc0/DBRAR Boot ROM Access Register The register is used to specify the control function and the data message passing for the on board Boot ROM. BIT 31 30:28 ATTRIBUTE R R/W BIT NAME BROMSEL Reserved. Fixed to 0. Boot ROM Size Select BROMSEL bits decides the size of the on board boot ROM device. 00x = No Boot ROM 010 = 8K 011 = 16K 100 = 32K 101 = 64K 110 = 128K 111 = 256K Loaded from EEPROM after Power-on reset. 27 R/W BROMRD BootROM Read Control When EESEL bit of register Dc4/DEEAR[31] is reset, setting this bit will perform the on-board boot ROM read operation with the reading address specified by bits BROMA. The bit BROMRD will be cleared automatically after BootROM read operation is completed. Bit BROMRD will not allow to be set high, even writing a logic 1 to BROMRD if the bit EESEL is set. 26 R/W BROMWR BootROM Write Control When EESEL bit of register Dc4/DEEAR[31] is reset, setting this bit will perform the on-board boot ROM write operation with the writing address specified by BROMA. This bit BROMWR will be cleared automatically after BootROM write operation is completed. The BROMWR will not allow to be set high, even writing a logic 1 to BROMWR if the bit EESEL is set. 25:8 7:0 R/W R/W BROMA BROMD Boot ROM Offset Address This field contains boot ROM offset address. Boot ROM Data BROMD are used to store the read/write data for the on board Boot ROM access when EESEL is reset to low. BROMD is of no meaning if the EESEL is set to high. DESCRIPTION - 73 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Dc4/DEEAR EEPROM Access Register The register is used to read or write information between system and EEPROM. BIT 31 ATTRIBUTE R/W BIT NAME EESEL DESCRIPTION EEPROM/BootROM Select 1: EEPROM access through Dc4/DEEAR is allowed. (default) 0: BootROM access through Dc0/DBRAR is allowed. 30 R/W StartEERW Start EEPROM Read/Write Access Set to 1, to start EEPROM RD/WR access. It will be cleared to 0 automatically, after access is complete. 29:28 R/W EERW EEPROM Read/Write Command 00: Read 01: Write 10: Write Protection Disable 11: Write Protection Enable 27:23 22:16 15:0 R R/W R/W ------EEOA EEData Reserved. Fixed to 0 EEPROM Offset Address This field contains EEPROM offset address. EEPROM Data EEPROM Data is used to store the read/write data for the on board EEPROM access when EESEL is set to high. EEData is of no meaning if the EESEL is set to low. Dc8/DMMAR MII Management Access Register The register is used to read or write information between system and MII management registers in transceiver. BIT 31 ATTRIBUTE R/W BIT NAME StartMDIORW DESCRIPTION Start MDIO Read/Write When set to 1, MDIO starts to read/ write PHY data. It will be clear automatically, when access completes. 30:29 R/W MDIORW MDIO RD/WR command 01: Write 10: Read (default) 00, 11: reserved - 74 - W89C841F/D Dc8/DMMAR MII Management Access Register, continued BIT 28:26 25:21 ATTRIBUTE R R/W BIT NAME ----PHYADD Reserved. Fixed to 0 PHY Address DESCRIPTION The PHY address must be the same as internal transceiver's PHY address setting. Deafult to 01h. 20:16 R/W REGADD PHY's Register Address Refer to MII Management Registers to access the dedicated register. 15:0 R/W REGData PHY Register Data PHY Register Data is used to store the read/write data for MII management registers in embedded transceiver. Dcc/DPA0 Physical Address Register 0 The register defines the first 32 bits of the 48 bits MAC address. The DPA0 value is loaded from EEPROM after hardware reset BIT 31:24 23:16 15:8 7:0 ATTRIBUTE R/W R/W R/W R/W BIT NAME PAR3 PAR2 PAR1 PAR0 Physical Address 3 The PAR3 defines the bit 24 - 31 of the MAC address. Physical Address 2 The PAR2 defines the bit 16 - 23 of the MAC address. Physical Address 1 The PAR1 defines the bit 8 - 15 of the MAC address. Physical Address 0 The PAR0 defines the bit 0 - 7 of the MAC address. DESCRIPTION Dd0/DPA1 Physical Address Register 1 The register defines the last 16 bits of the 48 bits MAC address. The DPA1 value is loaded from EEPROM after hardware reset BIT 31:16 15:8 ATTRIBUTE R R/W BIT NAME --PAR5 Reserved. Fixed at 0. Physical Address 5 The PAR5 defines the 40 - 47 bit of the 48 bit of the MAC address. 7:0 R/W PAR4 Physical Address 4 The PAR0 defines the 32 - 39 bit of the 48 bit of the MAC address. DESCRIPTION - 75 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Ddc/DRFCTV RXDMA Flow Control Threshold Value BIT 31:18 17:9 ATTRIBUTE R R/W BIT NAME --HTV Reserved. Fixed to 0. High Threshold Value When the receive byte count in the RX FIFO is greater than high threshold value, a pause packet with MAX pause time will be transmitted if bit TFCEN of register C1c/CNCR is set. Default value: 9'h180 8:0 R/W LTV Low Threshold Value When the receive byte count in the RX FIFO is less than low threshold value, a pause packet with MIN pause time will be transmitted if bit TFCEN of register C1c/CNCR is set. Default value: 9'h100 DESCRIPTION Df0/DFER Function Event Register This register is used for reporting of interrupt pending and power-management event detection in a CardBus system. A field in this register is set when the corresponding field in the Function Present State register changes its value. Writing "1" into a field clear the field. Writing "0" has no effect BIT 31:16 15 ATTRIBUTE R R/WC BIT NAME --INTR Reserved. Fixed to 0. Interrupt Event It is set when the interrupt is pending or FRS_INTR bit in the register Dfc/DFFER[15] is set, regardless the mask value. 14:5 4 R Sticky bit, R/WC ---GWAKE Reserved. Fixed to 0. General Wake-up Event It is set when the PRE_GWAKE bit in register Df8/DFPSR[4] changes its state from 0 to 1 or FRS_GWAKE bit in the Dfc/DFFER[4] is set, regardless the mask value. This bit is cleared by write 1 and writing 0 has no effect. This bit is default to 0 if PMEB generation from D3cold is not supported. If PMEB generation from D3cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Note: When W89C841F is configured into CardBus system, writing 1 to the field will clear this bit and the PME_Status bit in the register Fe0/FPMR1[15] too. Or writing 1 to the PME_Status bit in the register Fe0/FPMR1[15] will clear PME_Status bit and this GWAKE bit. DESCRIPTION 3:0 R --- Reserved. Fixed to 0. - 76 - W89C841F/D Df4/DFEMR Function Event Mask Register This register gives software the ability to control what events in the function cause the Status Changed interrupts or the host system Wakeup. This register controls the assertion of the signals INTAB and CSTSCHG in a CardBus system. BIT 31:16 15 ATTRIBUTE R R/W BIT NAME --INTR_ EN WKUP_ EN Reserved. Fixed to 0. Interrupt Enable Setting 1 enables the INTR in the function Event register to generate interrupt on the INTAB pin. Wake-up Enable Setting 1, enables the GWAKE bit in the register Df0/DFER to generate the Wakeup event on the CSTSCHG line if the GWAKE_En field is set together. When this bit reset to 0, the Wakeup function is disable. This bit defaults to 0 if PMEB generation from D3cold is not supported. If PMEB generation from D3cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. 13:5 4 R Sticky bit, R/W --GWAKE_ EN Reserved. Fixed to 0. General Wake-up Enable Setting 1, enables the GWAKE bit in the register Df0/DFER to generate the Wakeup event on the CSTSCHG line if the WKUP field is also set . When reset to 0, the Wakeup function is disable. This bit defaults to 0 if PMEB generation from D3cold is not supported. If PMEB generation from D3cold is supported, then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Note: When W89C841F is configured into CardBus system, setting or clearing PME_En bit in register Fe0/FPMR1[8] will also setting or clearing GWAKE_EN & WKUP_EN bits at the same time. Bits GWAKE_EN & WKUP_EN are allowed to be reset after setting PME_En bit. DESCRIPTION 14 Sticky bit, R/W 3:0 R --- Reserved. Fixed to 0. - 77 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Df8/DFPSR Function Present State Register This is read-only register reflects the current state of each condition that can cause a status change event. BIT 31:16 15 ATTRIBUTE R R BIT NAME ---PRE_INT Reserved. Fixed to 0. Present Interrupt Status It reflects the current state of interrupt requests regardless of the mask value. It is set when the Ethernet function has a pending interrupt and cleared when the software driver acknowledges all active interrupts from register C14/CISR. 14:5 4 R R ---PRE_ GWAKE Reserved. Fixed to 0. Present General Wake-up Status: It reflects the current state of the wake-up event. This bit is cleared when either the General Wake-up Event in the function event register is cleared, or when the PME_Status bit in the register Fe0/FPMR1[15] is cleared. Reserved. Fixed to 0. DESCRIPTION 3:0 R ---- Dfc/DFFER Function Force Event Register This register is used to generate interrupt or wake-up event. BIT 31:16 15 ATTRIBUTE R W BIT NAME --FRS_INTR Reserved. Fixed to 0. Force Interrupt Event: Writing 1 to this field sets the INTR bit in the register Df0/DFER. PRE_INTR bit in the register Df8/DFPSR[15] is not affected and continues to reflect the current state of the functional interrupt. Writing 0 has no effect. 14:5 4 R W --FRS_ GWAKE Reserved. Fixed to 0. Force General Wake-up Event: Writing 1 to this field sets the GWAKE bit in the register Df0/DFER. PRE_GWAKE bit in the register Df8/DFPSR[4] is not affected and continues to reflect the current state of the Wakeup request. Writing 0 has no effect. Reserved. Fixed to 0. DESCRIPTION 3:0 R --- - 78 - W89C841F/D MII Management Registers W89C841F supports MDC/MDIO interface to access MII management registers located in embedded PHYceiver. The following table list all of the MII Management registers supported by W89C841F. ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h - 0Fh 10h 11h 12h 13h 14h 15h Status Register PHY Identifier Register 1 PHY Identifier Register 2 Auto Negotiation Advertisement Register Auto Negotiation Link Partner Ability Register Auto Negotiation Expansion Register Next Page Transmit Register Link Partner Next Page Register IEEE Reserved PHY Specific Control Register Port Configuration Register PHY Specific Status Register Global Interrupt Enable Register Global Interrupt Status Register Receive Error Counter REGISTER NAME Control Register DEFAULT 3100h 7849h 0022h E011h 05E1h 01E1h 0004h 2001h 0000h FFFFh 0680h 0026h 000Fh 0000h 0000h 0000h - 79 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Control (Register 0h) BIT(S) 0.15 NAME RST RESET 1 - PHY Reset 0 - Normal operation 0.14 LPBK Loop Back Enable 1 - Enable loopback mode 0 - Disable Loopback mode 0.13 SPEED_LSB Speed Selection LSB 0.13 0 0 1 1 0.12 ANEN 0 1 0 1 10 Mbits/s 100 Mbits/s 1000 Mbits/s Reserved R/W 1h R/W 1h R/W 0h DESCRIPTION R/W R/W SC DEFAULT 0h Auto Negotiation Enable 1 - Enable auto negotiation process 0 - Disable Auto negotiation process 0.11 PDN Power Down Enable 1 - Power Down 0 - Normal Operation R/W 0h 0.10 ISO Isolate AD2105 from Network 1 - Isolate PHY from MII/RMII 0 - Normal Operation R/W 0h 0.9 ANEN_ RST Restart Auto Negotiation 1 - Restart Auto Negotiation Process 0 - Normal Operation Duplex Mode 1 - Full Duplex mode 0 - Half Duplex mode R/W SC R/W 0h 0.8 DPLX 1h 0.7 COLTST Collision Test 1 - Enable COL signal test 0 - Disable COL signal test R/W 0h 0.6 0.5:0 SPEED_MSB Reserved Speed Selection MSB Not Used RO RO 0h 00h - 80 - W89C841F/D Status (Register 1h) BIT(S) 1.15 1.14 1.13 1.12 1.11 1.10 1.9:7 1.6 1.5 NAME CAP_T4 CAP_TXF CAP_TXH CAP_TF CAP_TH CAP_T2 Reserved CAP_SUPR AN_COMP DESCRIPTION 100Base-T4 Capable 100Base-X Full Duplex Capable 100Base-X Half Duplex Capable 10M Full Duplex Capable 10M Half Duplex Capable 100Base-T2 Capable Ignored when read MF Preamble Suppression Capable Auto Negotiation Complete 1 - Auto Negotiation process completed 0 - Auto Negotiation process not completed 1.4 REM_FLT Remote Fault Detect 1 - Remote Fault detected 0 - Remote Fault not detected 1.3 CAP_ANEG Auto Negotiation Ability 1 - Capable of auto negotiation 0 - Not capable of auto negotiation 1.2 LINK Link Status 1 - Link is up 0 - Link is down 1.1 JAB Jabber Detect 1 - Jabber condition detected 0 - Jabber condition not detected 1.0 EXTREG Extended Capability 1 - Extended register set 0 - No extended register set RO 1h RO, LH 0h RO, LL 0h RO 1h RO 0h R/W RO RO RO RO RO RO RO RO RO DEFAULT 0h 1h 1h 1h 1h 0h 0h 1h 0h PHY Identifier Register (Register 2h) BIT(S) 2.15:0 NAME PHY-ID[15:0] DESCRIPTION IEEE Address R/W RO DEFAULT 0022 PHY Identifier Register (Register 3h) BIT(S) 315:0 NAME PHY-ID[15:0] DESCRIPTION IEEE Address/Model No./Rev. No. R/W RO DEFAULT E011 - 81 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Advertisement (Register 4h) BIT(S) 4.15 4.14 4.13 NAME NP Reserved RF DESCRIPTION Next Page Reserved Remote Fault 1 - Remote Fault has been detected 0 - No remote fault has been detected Reserved Asymmetric Pause Direction. Bit[11:10] Capability 00 No Pause 01 Symmetric PAUSE Asymmetric PAUSE toward Link Partner Both Symmetric PAUSE and Asymmetric PAUSE toward local device Pause Operation for Full Duplex Technology Ability for 100Base-T4 100Base-TX Full Duplex 1 - Capable of 100M Full duplex operation 0 - Not capable of 100M Full duplex operation 100Base-TX Half Duplex 1 - Capable of 100M operation 0 - Not capable of 100M operation 10BASE-T Full Duplex 1 - Capable of 10M Full Duplex operation 0 - Not capable of 10M full duplex operation 10Base-T Half Duplex 1 - Capable of 10M operation 0 - Not capable of 10M operation R/W RO RO R/W DEFAULT 0h 0h 0h 4.12 4.11 IEEE Reserved ASM_DIR RO R/W 0h 0h 4.10 4.9 4.8 PAUSE T4 TX_FDX R/W RO R/W 1h 0h 1h 4.7 TX_HDX R/W 1h 4.6 10_FDX R/W 1h 4.5 10_HDX R/W 1h 4.4:0 Selector Field These 5 bits are hardwired to 00001b. RO 01h Auto Negotiation Link Partner Ability (Register 5h) BIT(S) 5.15 NAME NPAGE DESCRIPTION Next Page 1 - Capable of next page function 0 - Not capable of next page function Acknowledge 1 - Link Partner acknowledges reception of the ability data word 0 - Not acknowledged Remote Fault 1 - Remote Fault has been detected 0 - No remote fault has been detected Reserved R/W RO DEFAULT 0h 5.14 ACK RO 0h 5.13 RF RO 0h 5.12:11 IEEE Reserved RO 0h - 82 - W89C841F/D Auto Negotiation Link Partner Ability (Register 5h), continued BIT(S) 5.11 5.10 5.9 5.8 NAME LP_DIR LP_PAU LP_T4 LP_FDX DESCRIPTION Link Partner Asymmetric Pause Direction. Link Partner Pause Capability Link Partner Technology Ability for 100Base-T4 100Base-TX Full Duplex 1 - Capable of 100M Full duplex operation 0 - Not capable of 100M Full duplex operation R/W RO RO RO RO DEFAULT 0h 0h 0h 1h 5.7 LP_HDX 100Base-TX Half Duplex 1 - Capable of 100M operation 0 - Not capable of 100M operation RO 1h 5.6 LP_F10 10BASE-T Full Duplex 1 - Capable of 10M Full Duplex operation 0 - Not capable of 10M full duplex operation RO 1h 5.5 LP_H10 10Base-T Half Duplex 1 - Capable of 10M operation 0 - Not capable of 10M operation RO 1h 5.4:0 Selector Field Encoding Definitions. RO 1h Auto Negotiation Expansion Register (Register 6h) BIT(S) 6.15:5 6.4 NAME Reserved PFAULT Reserved Parallel Detection Fault 1 - Fault has been detected 0 - No Fault Detect 6.3 LPNPABLE Link Partner Next Page Able 1 - Link Partner is next page capable 0 - Link Partner is not next page capable 6.2 6.1 NPABLE PGRCV Next Page Able Defaults to 1, indicating AD2105 is next page able. Page Received 1 - A new page has been received 0 - No new page has been received 6.0 LPANABLE Link Partner Auto Negotiation Able 1 - Link Partner is auto negotiable 0 - Link Partner is not auto negotiable RO, LH RO 0h 0h RO 1h DESCRIPTION R/W RO RO, LH RO 0h DEFAULT 000h 0h - 83 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Next Page Transmit Register (Register 7h) BIT(S) 7.15 7.14 7.13 7.12 7.11 7.10:0 NAME TNPAGE Reserved TMSG TACK2 TTOG TFLD[10:0] DESCRIPTION Transmit Next Page Transmit Code Word Bit 15 Reserved Transmit Code Word Bit 14 Transmit Message Page Transmit Code Word Bit 13 Transmit Acknowledge 2 Transmit Code Word Bit 12 Transmit Toggle Transmit Code Word Bit 11 Transmit Message Field Transmit Code Word Bit 10...0 R/W 001h RO 0h R/W 0h R/W 1h RO 0h R/W R/W DEFAULT 0h Link Partner Next Page Register (Register 8h) BIT(S) 8.15 8.14 8.13 8.12 8.11 8.10:0 NAME PNPAGE PACK PMSGP PACK2 PTOG PFLD[10:0] DESCRIPTION Link Partner Next Page Receive Code Word Bit 15 Link Partner Acknowledge Receive Code Word Bit 14 Link Partner Message Page Receive Code Word Bit 13 Link Partner Acknowledge 2 Receive Code Word Bit 12 Link Partner Toggle Receive Code Word Bit 11 Link Partner Message Field Receive Code Word Bit 11 RO 000h RO 0h RO 0h RO 0h RO 0h R/W RO DEFAULT 0h - 84 - W89C841F/D Channel and 10M Configuration Register (Register 10h) BIT(S) 16. 15:12 16.11 NAME RESERVED IFSEL Reserved Interface Select. 0: MII 1: RMII Enable Register 8 to Store Next Page Information. 1 - Store Next Page in Register 8 0 - Store Next Page in Register 5 Cross Over Auto Detect Enable. 0: Disable 1: Enable Disable Power Management Feature. 0: Enable 1: Disable Enable Receive Jabber Monitor. 0: Disable 1: Enable Medium Detect Voltage Control (Peak to Peak) 00: 50 mV 01: 100 mV 10: 150 mV 11: 200 mV Reduce 10M Driver to 62mA 1 = 62 mA 0 = Normal Auto Polarity Disable 1 = Auto Polarity Function Disabled 0 = Normal Disable Transmit Jabber 1 - Disable Transmit Jabber Function 0 - Enable Transmit Jabber Function Enable Extended Distance 1 - Lower 10BASE-T Receive threshold 0 - Normal 10BASE-T Receive threshold Force 10M Receive Good Link 1 - Force Good Link 0 - Normal Operation DESCRIPTION R/W RO RO DEFAULT 0h 0h 16.10 ENREG8 R/W 1h 16.9 XOVEN R/W 1h 16.8 DISPMG R/W 0h 16.7 ENRJAB R/W 1h 16.6:5 VTHR[1:0] R/W 0h 16.4 DRV62MA R/W 0h 16.3 APDIS R/W 0h 16.2 DISTJAB R/W 0h 16.1 ETH R/W 0h 16.0 FGDLNK R/W 0h - 85 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D PHY 100M Module Control Register (Register 11h) BIT(S) 17. 15:8 17.7 SELFX Fiber Select 1: Fiber Mode 0: TP Mode 17.6:5 17.4 FXTSEL[1:0] DISSCR Fiber Control Signal Disable Scrambler 1 - Disable Scrambler 0 - Enable Scrambler 17.3 ENFEFI Enable FEFI 1 - Enable FEFI 0 - Disable FEFI 17.2:1 17.0 BSLIMT[1:0] ADFS Base Line Threshold Adjust AD Full Scale Adjust R/W R/W 1h 0h R/W pin R/W R/W 1h 0h R/W 0h NAME Reserved Reserved DESCRIPTION R/W RO DEFAULT 0h PHY Specific Status Register (Register 12h) BIT(S) 18. 15:13 18.12 FXEN Fiber Enable. Only Changed when PHY Reset 0: TX 1: FX mode OR'ed result of PI_SELFX and 17.9 (SELFX) 18.11 XOVER Cross Over. 0: MDI mode 1: MDIX mode 18.10 JAB Real Time Jabber Status 1 - Jabber 0 - No Jabber 18.9 POLAR Polarity. 0: Normal Polarity 1: Polarity Reversed RO 0h RO 0h RO 0h RO pin NAME RESERVED Reserved DESCRIPTION R/W RO DEFAULT 0h - 86 - W89C841F/D PHY Specific Status Register (Register 12h), continued BIT(S) 18.8 NAME PAUOUT DESCRIPTION Pause Out capability. Disabled when Half Duplex. 0: Lack of Pause Out capability 1: Has Pause Out capability R/W RO DEFAULT 0h 18.7 PAUIN Pause In capability. Disabled when Half Duplex. 0: Lack of Pause In capability 1: Has Pause In capability RO 0h 18.6 DUPLEX Operating Duplex 1 - Full Duplex 0 - Half Duplex RO 0h 18.5 SPEED Operating Speed 1 - 100Mb/s 0 - 10Mb/s RO 0h 18.4 LINK Real Time Link Status 1 - Link Up 0 - Link Down RO 0h 18.3 RECPAU Pause Recommend Value. Only Changed when PHY Reset. This bit is disabled automatically when RECDUP is 0. 0: Pause Disable 1: Pause Enable RO 1h 18.2 RECDUP Duplex Recommended Value. Only Changed when PHY Reset 1: Full Duplex 0: Half Duplex RO 1h 18.1 RECSPD Speed Recommend Value. Only Changed when PHY Reset 1: 100M 0: 10M RO 1h 18.0 RECANEN Recommended Auto Negotiation Value. Only Changed when PHY Reset RO 1h - 87 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Interrupt Enable Register (Register 13h) BIT(S) 19.15 NAME XOVCHG DESCRIPTION Cross Over mode Changed Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.14 SPDCHG Speed Changed Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.13 DUPCHG Duplex Changed Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.12 PGRCHG Page Received Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.11 LNKCHG Link Status Changed Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.10 SYMERR Symbol Error Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.9 FCAR False Carrier Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.8 FOURUN Fifo Over/UnderRun Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.7 JABINT Jabber Interrupt Enable 1 - Interrupt Enable 0 - Interrupt Disable 19.6:0 Reserved Reserved RO 00h R/W 0h R/W 0h R/W 0h R/W 0h R/W 0h R/W 0h R/W 0h R/W 0h R/W R/W DEFAULT 0h - 88 - W89C841F/D Interrupt Status Register (Register 14h) BIT(S) 20.15 NAME XOVCHG DESCRIPTION Cross Over mode Changed 1 - Cross Over mode Changed 0 - Cross Over mode Not Changed Speed Changed 1 - Speed Changed 0 - Speed Not Changed Duplex Changed 1 - Duplex Changed 0 - Duplex not changed Page Received 1 - Page Received 0 - Page not received Link Status Changed 1 - Link Status Changed 0 - Link Status not Changed Symbol Error 1 - Symbol Error 0 - No symbol Error False Carrier 1 - False Carrier 0 - No false carrier Will be high whenever Link is Failed. Fifo Over/UnderRun 1 - FIFO Over/Uner Run 0 - No FIFO Over/Under Run Jabber 1 - Jabber 0 - No Jabber Reserved R/W COR DEFAULT 0h 20.14 SPDCHG COR 0h 20.13 DUPCHG COR 0h 20.12 PGRCHG COR 0h 20.11 LNKCHG COR 0h 20.10 SYMERR COR 0h 20.9 FCAR COR 0h 20.8 FOURUN COR 0h 20.7 JABINT COR 0h 20.6:0 Reserved COR 00h Receive Error Counter Register (Register 15h) BIT(S) 21.15:0 NAME ERB[15:0] DESCRIPTION Error Counter. Includes False Carrier Jabber Symbol Error FIFO Under/Over Run Link Code Word Error Error Start of Stream Error End of Stream R/W RO DEFAULT 0000h - 89 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D 10. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage SYMBOL TA TS VCC_core VCC_IO VIN VOUT MIN. 0 -55 2.25 3.0 VSS VSS MAX. 70 125 2.75 3.6 5 + 0.5 3.6 V V UNIT C C V Power Supply (TA = 0 C to 70 C) PARAMETER Power Supply Current (D0 state) Power Supply Current (D1) Power Supply Current (D3 hot) Power Supply Current (D3 cold) SYMBOL IDD0 IDD1 IDD1 IDD1 CONDITION VCC_core = 2.5V VCC_IO = 3.3V VCC_core = 2.5V VCC_IO = 3.3V VCC_core = 2.5V VCC_IO = 3.3V VCC_core = 2.5V VCC_IO = 3.3V MAX. 210 178 178 158 UNIT mA mA mA mA DC Characteristics (VCC_core = 2.25V to 2.75V, VCC = 3.0V to 3.6V, VSS = 0V, TA = 0 C to 70 C) PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current SYMBOL VIL VIH VOL VOH IIL IIH CONDITION MIN. 1.7 MAX. 0.7 UNIT V V V V A A IOL = 4.0 mA IOH = -4.0 mA VIN = VCC VIN = 0V 0 1.85 -10 -10 0.4 3.6 10 10 - 90 - W89C841F/D AC Characteristics (VCC_core = 2.5V, VCC_IO = 3.3V, VSS = 0 V, TA = 0 C to 70 C) PCI Slave Read Transaction 0 CLK FRAME# AD[31::0] C/BE[3:0]# IRDY# TRDY# T9 T1 T2 ADDRESS BUS CMD 1 2 3 T11 T3 BE#'s DATA T4 T5 T6 T12 T13 DEVSEL# T7 T8 T10 OUTPUT PAR IDSEL# INPUT T14 T15 PARAMETERS PCI Input Signal Set-up Time* PCI Input Signal Hold Time* BE Byte Enable Set-up Time BE Byte Enable Hold Time IRDY# Set-up Time IRDY# Hold Time PAR Input Set-up Time PAR Input Hold Time DEVSEL# Driven Time DEVSEL# Hold Time Output Data Hold Time TRDY# Driven Time TRDY# Hold Time PAR Output Driven Time PAR Output Hold Time SYMBOL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 MIN. 7 2 7 2 7 2 7 2 9 9 9 9 9 9 9 TYP. MAX. UNIT nS nS nS nS nS nS nS nS 10 10 10 10 10 10 10 11 11 11 11 11 11 11 nS nS nS nS nS nS nS Note: address, command, and FRAME# for slave access, IDSEL# for configuration read transaction - 91 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D AC Characteristics, continued PCI Slave Write Transaction 0 CLK T1 1 2 3 FRAME# T2 T11 DATA DATA T12 AD[31::0] C/BE[3:0]# IRDY# TRDY# DEVSEL# ADDRESS T3 BUS CMD BE#'s T4 T5 T6 T9 T13 T14 T7 T8 T10 INPUT PAR IDSEL# INPUT T15 T16 T18 PERR# T17 PARAMETERS PCI Input Signal Set-up Time* PCI Input Signal Hold Time* BE Byte Enable Set-up Time BE Byte Enable Hold Time IRDY# Set-up Time IRDY# Hold Time PAR Input Set-up Time PAR Input Hold Time DEVSEL# Driven Time DEVSEL# Hold Time Input Data Set-up Time Input Data Hold Time TRDY# Driven Time TRDY# Hold Time PAR Input Set-up Time PAR Input Hold Time PERR# Driven Time** PERR# Hold Time** SYMBOL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 MIN. 7 2 7 2 7 2 7 2 9 9 7 2 9 9 7 2 9 9 TYP. MAX. 10 10 11 11 10 10 11 11 10 10 11 11 UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS Note: Address, command, and FRAME# for slave access, IDSEL# for configuration read transaction **PERR# will be asserted if the parity error event occurred. - 92 - W89C841F/D AC Characteristics, continued PCI Transaction, Termination Disconnect-C/Retry Type 0 1 2 3 4 15 16 17 18 19 CLK FRAME# AD[31::0] C/BE[3::0]# IRDY# TRDY# DEVSEL# STOP# T2 T3 T1 ADDRESS BUS CMD BE#'s PARAMETERS FRAME# Deasserted from Clock 15 Clock 16 to STOP# Asserted Time Clock 18 to STOP# and DEVSEL# Hold Time Notes: SYMBOL T1 T2 T3 MIN. 2 9 9 TYPICAL MAX. UNIT nS 10 10 11 11 nS nS 1) The other timing requirements for PCI input signal are as the read transaction timing. 2) T1, T2 and T3 are used for the disconnect type C (host try to transfer more than one data phase). - 93 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D AC Characteristics, continued Target-Abort Type 0 1 2 3 4 5 6 7 8 9 CLK FRAME# AD[31::0] C/BE[3::0]# IRDY# TRDY# DEVSEL# T3 T2 T1 ADDRESS BUS CMD BE#'s STOP# PARAMETERS FRAME# Deasserted from Clock 15 Clock 4 to DEVSEL# Hold Time Clock 6 to STOP# Hold Time Notes: SYMBOL T1 T2 T3 MIN. 2 9 9 TYPICAL MAX. UNIT nS 10 10 11 11 nS nS 1) The other timing requirements for PCI input signal are as the read transaction timing. 2) T2 and T3 are used for the target abort type (host addressing error). - 94 - W89C841F/D AC Characteristics, continued Boot ROM Read Cycle Timing TRC BtAdd[17:0] TH BtCSB Ts BtOEB VIH BtWEB BtData[7:0] Data Valid PARAMETERS Read Cycle Time Data Set-up Time Data Hold Time SYMBOL TRC TS TH MIN. MAX. 330 UNIT nS nS nS 5 2 - - 95 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D AC Characteristics, continued Boot Rom Write Cycle Timing TAS TAH BtAdd[17:0] TCS TCP BtCSB BtWEB TWP BtOEB VIH TDS BtData[7:0] Data Valid PARAMETERS Address Set-up Time Address Hold Time BtWEB and BtCSB Set-up Time BtCSB Pulse Width BtWEB Pulse Width Data Set-up Time SYMBOL TAS TAH TCS TCP TWP TDS MIN. - MAX. 150 60 88 120 600 120 UNIT nS nS nS nS nS nS - 96 - W89C841F/D AC Characteristics, continued Serial EEPROM Timing EC ES EC EK T1 T5 T3 T7 T4 T2 T6 ED EI T8 ED EO PARAMETERS EECS Asserted to EECK EECS Hold from EECK EECK OFF Time EECK ON Time EECK Clock Period EEDI Set-up Time EEDI Hold Time EEDO Output Delay SYMBOL T1 T2 T3 T4 T5 T6 T7 T8 TYP. 610 3 600 600 1.2 600 600 100 UNIT nS nS nS nS uS nS nS nS - 97 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D AC Characteristics, continued PHYceiver MII Timing T4 RX_CLK RXD[3:0], RX_DV, RX_ER T1 TX_CLK TXD[3:0], TX_EN, TX_ER T2 T3 PARAMETERS Output Delay for RXD, RX_DV, RX_ER Set-up Time for TXD, TX_EN, TX_ER Hold Time for TXD, TX_EN, TX_ER Clock Cycle (100M) (10M) SYMBOL T1 T2 T3 T4 TYP. 5 15 0 40 400 UNIT nS nS nS nS - 98 - W89C841F/D AC Characteristics, continued MAC Controller MII Timing T4 TX_CLK TXD[3:0], TX_EN, TX_ER T1 RX_CLK RXD[3:0], RX_DV, RX_ER T2 T3 PARAMETERS Output Delay for TXD, TX_EN, TX_ER Setup Time for RXD, RX_DV, RX_ER Hold Time for RXD, RX_DV, RX_ER Clock Cycle (100M) (10M) SYMBOL T1 T2 T3 T4 TYP. 7 10 10 40 400 UNIT nS nS nS nS - 99 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D 11. PACKAGE DIMENSIONS W89C841F: 128L QFP (14 x 20 x 2.75 mm footprint 3.2 mm) HD D 128 1 103 102 EH E 38 39 b 65 64 e c A A2 See Detail F Seating Plane A1 y L L1 Detail F Symbol Dimension in inch Dimension in mm M in. N o m . Max. M in. N o m . Max. 3.40 0.10 A A1 A2 b c D E e HD HE L L1 y 0.134 0.004 0.101 0.006 0.004 0.547 0.783 0.107 0.008 0.006 0.551 0.787 0.020 0.669 0.905 0.023 0.055 0.677 0.913 0.031 0.063 0.685 0.921 0.039 0.071 0.004 0 12 0 17.00 23.00 0.60 1.40 0.113 0.010 0.010 0.555 0.791 2.57 0.15 0.10 13.90 19.90 2.72 0.20 0.15 14.00 20.00 0.50 17.20 23.20 0.80 1.60 2.87 0.25 0.25 14.10 20.10 17.40 23.40 1.00 1.80 0.10 12 - 100 - W89C841F/D Package dimensions, continued W89C841D: 128L LQFP (14 x 20 x 1.4 mm) HD D 128 103 1 102 E HE 38 65 39 e b 64 c A A2 See Detail F Seating Plane A1 y L L1 Detail F Dimension in inch Dimension in mm Sym b o l M in. N o m . Max. M in. N o m . Max. 0.063 0.002 0.053 0.006 0.004 0.547 0.783 0.055 0.008 0.006 0.551 0.787 0.020 0.626 0.862 0.018 0.630 0.866 0.024 0.039 0.004 0 12 0 0.634 0.870 0.030 15.90 21.90 0.45 0.057 0.011 0.010 0.555 0.791 0.05 1.35 0.15 0.10 13.90 19.90 1.40 0.20 0.15 14.00 20.00 0.50 16.00 22.00 0.60 1.00 0.10 12 16.10 22.10 0.75 1.45 0.27 0.25 14.10 20.10 1.60 A A1 A2 b c D E e HD HE L L1 y - 101 - Publication Release Date: October 18, 2001 Revision A3 W89C841F/D Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East. Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 102 - |
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